google/gru: add MAX_SDRAM_FREQ config to choose max ddr freq

Gru/Kevin use 933 MHz (actually 928 MHz for better jitter) as max sdram
frequency, while bob uses 800 MHz.

It's normal some variants can't meet 928 MHz SI requirement and hence
have to use a lower freq as spec.

BUG=chrome-os-partner:61001
BRANCH=gru
TEST=check dpll is 800 MHz on bob

Change-Id: I6d19a351f25d1f48547715ce57c3a87d9505f6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8176bfea52422c713f144ffec419752aeca66db2
Original-Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/420208
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55)
Original-Reviewed-on: https://chromium-review.googlesource.com/448277
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18581
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Shunqian Zheng 2017-01-10 11:10:46 +08:00 committed by Patrick Georgi
parent c1749718d1
commit a24c81cd30
13 changed files with 6298 additions and 1 deletions

View File

@ -91,6 +91,13 @@ config MAINBOARD_PART_NUMBER
default "Gru" if BOARD_GOOGLE_GRU
default "Kevin" if BOARD_GOOGLE_KEVIN
# The default max sdram freq is 933M(actually 928M dpll), and
# 800M is another choice.
config MAX_SDRAM_FREQ
int
default 800 if BOARD_GOOGLE_BOB
default 933
config GBB_HWID
string
depends on CHROMEOS

View File

@ -13,7 +13,7 @@
## GNU General Public License for more details.
##
subdirs-y += sdram_params/
subdirs-y += sdram_params_$(CONFIG_MAX_SDRAM_FREQ)/
bootblock-y += bootblock.c
bootblock-y += chromeos.c

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@ -0,0 +1,27 @@
##
## This file is part of the coreboot project.
##
## Copyright 2017 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
sdram-params :=
sdram-params += sdram-lpddr3-samsung-2GB-24EB
sdram-params += sdram-lpddr3-micron-2GB
sdram-params += sdram-lpddr3-samsung-4GB-04EB
sdram-params += sdram-lpddr3-micron-4GB
$(foreach params,$(sdram-params), \
$(eval cbfs-files-y += $(params)) \
$(eval $(params)-file := $(params).c:struct) \
$(eval $(params)-type := struct) \
$(eval $(params)-compression := $(CBFS_COMPRESS_FLAG)) \
)

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