GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AGESA boards: Clean up Ids.h and Filecode.h includes 

Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-09-10 23:44:50 +03:00
parent b7959b5921
commit a257efcfcc
78 changed files with 0 additions and 128 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/amd/bettong/BiosCallOuts.c
View File

@ -19,7 +19,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/pi/00660F01/chip.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

1
src/mainboard/amd/bettong/OemCustomize.c
View File

@ -17,7 +17,6 @@
#include <PlatformMemoryConfiguration.h>
#include <boardid.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */

1
src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
View File

@ -18,7 +18,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <device/azalia.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

1
src/mainboard/amd/db-ft3b-lc/OemCustomize.c
View File

@ -17,7 +17,6 @@
#include <northbridge/amd/pi/agesawrapper.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */

1
src/mainboard/amd/dinar/BiosCallOuts.c
View File

@ -17,7 +17,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Ids.h"
#include "SB700.h"
#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
#include <stdlib.h>

2
src/mainboard/amd/dinar/buildOpts.c
View File

@ -24,8 +24,6 @@
*/
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
/* AGESA will check the OEM configuration during preprocessing stage,
* coreboot enable -Wundef option, so we should make sure we have all contanstand defined

2
src/mainboard/amd/dinar/gpio.c
View File

@ -13,12 +13,10 @@
* GNU General Public License for more details.
*/
#include "Filecode.h"
#include "Hudson-2.h"
#include "AmdSbLib.h"
#include "gpio.h"
#define FILECODE UNASSIGNED_FILE_FILECODE
#ifndef SB_GPIO_REG01
#define SB_GPIO_REG01 1

1
src/mainboard/amd/inagua/OemCustomize.c
View File

@ -20,7 +20,6 @@
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**

2
src/mainboard/amd/inagua/buildOpts.c
View File

@ -26,8 +26,6 @@
*/
#include <stdlib.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

1
src/mainboard/amd/lamar/BiosCallOuts.c
View File

@ -16,7 +16,6 @@
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

1
src/mainboard/amd/lamar/OemCustomize.c
View File

@ -16,7 +16,6 @@
#include <northbridge/amd/pi/agesawrapper.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {

1
src/mainboard/amd/olivehill/BiosCallOuts.c
View File

@ -17,7 +17,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

3
src/mainboard/amd/olivehill/OemCustomize.c
View File

@ -15,14 +15,11 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
{

2
src/mainboard/amd/olivehill/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE

1
src/mainboard/amd/olivehillplus/BiosCallOuts.c
View File

@ -16,7 +16,6 @@
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

1
src/mainboard/amd/olivehillplus/OemCustomize.c
View File

@ -15,7 +15,6 @@
#include <northbridge/amd/pi/agesawrapper.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */

1
src/mainboard/amd/parmer/BiosCallOuts.c
View File

@ -17,7 +17,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

3
src/mainboard/amd/parmer/OemCustomize.c
View File

@ -15,14 +15,11 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)

2
src/mainboard/amd/parmer/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE

1
src/mainboard/amd/persimmon/OemCustomize.c
View File

@ -20,7 +20,6 @@
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/**
* OemCustomizeInitEarly

2
src/mainboard/amd/persimmon/buildOpts.c
View File

@ -26,8 +26,6 @@
*/
#include <stdlib.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

1
src/mainboard/amd/south_station/OemCustomize.c
View File

@ -20,7 +20,6 @@
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**

2
src/mainboard/amd/south_station/buildOpts.c
View File

@ -26,8 +26,6 @@
*/
#include <stdlib.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

1
src/mainboard/amd/thatcher/BiosCallOuts.c
View File

@ -17,7 +17,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

3
src/mainboard/amd/thatcher/OemCustomize.c
View File

@ -15,14 +15,11 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)

2
src/mainboard/amd/thatcher/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE

1
src/mainboard/amd/torpedo/BiosCallOuts.c
View File

@ -16,7 +16,6 @@
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Ids.h"
#include "Hudson-2.h"
#include <stdlib.h>
#include <southbridge/amd/cimx/sb700/gpio_oem.h>

1
src/mainboard/amd/torpedo/OemCustomize.c
View File

@ -21,7 +21,6 @@
#include <PlatformMemoryConfiguration.h>
#include "amdlib.h"
#define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)

2
src/mainboard/amd/torpedo/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

2
src/mainboard/amd/torpedo/gpio.c
View File

@ -13,12 +13,10 @@
* GNU General Public License for more details.
*/
#include "Filecode.h"
#include "SbPlatform.h"
#include "gpio.h"
#include "vendorcode/amd/cimx/sb900/AmdSbLib.h"
#define FILECODE UNASSIGNED_FILE_FILECODE
#ifndef SB_GPIO_REG01
#define SB_GPIO_REG01 1

3
src/mainboard/amd/union_station/OemCustomize.c
View File

@ -15,16 +15,13 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**

2
src/mainboard/amd/union_station/buildOpts.c
View File

@ -26,8 +26,6 @@
*/
#include <stdlib.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

3
src/mainboard/asrock/e350m1/OemCustomize.c
View File

@ -15,16 +15,13 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**

2
src/mainboard/asrock/e350m1/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

1
src/mainboard/asrock/imb-a180/BiosCallOuts.c
View File

@ -18,7 +18,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include <stdlib.h>

3
src/mainboard/asrock/imb-a180/OemCustomize.c
View File

@ -15,14 +15,11 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
{

2
src/mainboard/asrock/imb-a180/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE

1
src/mainboard/asus/f2a85-m/OemCustomize.c
View File

@ -21,7 +21,6 @@
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)

1
src/mainboard/asus/f2a85-m/buildOpts.c
View File

@ -41,7 +41,6 @@
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE

1
src/mainboard/bap/ode_e20XX/BiosCallOuts.c
View File

@ -17,7 +17,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

3
src/mainboard/bap/ode_e20XX/OemCustomize.c
View File

@ -15,14 +15,11 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device Number 2, Function 4) */

2
src/mainboard/bap/ode_e20XX/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE

1
src/mainboard/bap/ode_e21XX/BiosCallOuts.c
View File

@ -16,7 +16,6 @@
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

1
src/mainboard/bap/ode_e21XX/OemCustomize.c
View File

@ -15,7 +15,6 @@
#include <northbridge/amd/pi/agesawrapper.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */

1
src/mainboard/biostar/am1ml/BiosCallOuts.c
View File

@ -19,7 +19,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include <stdlib.h>

3
src/mainboard/biostar/am1ml/OemCustomize.c
View File

@ -15,14 +15,11 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
{

2
src/mainboard/biostar/am1ml/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE

1
src/mainboard/elmex/pcm205400/OemCustomize.c
View File

@ -20,7 +20,6 @@
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/**
* OemCustomizeInitEarly

2
src/mainboard/elmex/pcm205400/buildOpts.c
View File

@ -26,8 +26,6 @@
*/
#include <stdlib.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the cpu family. */

1
src/mainboard/gizmosphere/gizmo/OemCustomize.c
View File

@ -16,7 +16,6 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"

2
src/mainboard/gizmosphere/gizmo/buildOpts.c
View File

@ -28,8 +28,6 @@
#include <stdlib.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

1
src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
View File

@ -17,7 +17,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "imc.h"

3
src/mainboard/gizmosphere/gizmo2/OemCustomize.c
View File

@ -15,14 +15,11 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
{

2
src/mainboard/gizmosphere/gizmo2/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE

1
src/mainboard/hp/abm/BiosCallOuts.c
View File

@ -18,7 +18,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "Ids.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include <stdlib.h>

3
src/mainboard/hp/abm/OemCustomize.c
View File

@ -16,14 +16,11 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
{

2
src/mainboard/hp/abm/buildOpts.c
View File

@ -32,8 +32,6 @@
#include <stdlib.h>
#include "AGESA.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE

1
src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
View File

@ -21,7 +21,6 @@
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)

1
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
View File

@ -43,7 +43,6 @@
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE

1
src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
View File

@ -21,7 +21,6 @@
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/**
* OemCustomizeInitEarly

1
src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
View File

@ -41,7 +41,6 @@
#include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h>
#include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h>
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE

1
src/mainboard/lenovo/g505s/OemCustomize.c
View File

@ -21,7 +21,6 @@
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)

1
src/mainboard/lenovo/g505s/buildOpts.c
View File

@ -43,7 +43,6 @@
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE

3
src/mainboard/lippert/frontrunner-af/OemCustomize.c
View File

@ -15,16 +15,13 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**

2
src/mainboard/lippert/frontrunner-af/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

3
src/mainboard/lippert/toucan-af/OemCustomize.c
View File

@ -15,16 +15,13 @@
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**

2
src/mainboard/lippert/toucan-af/buildOpts.c
View File

@ -27,8 +27,6 @@
#include <stdlib.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

1
src/mainboard/msi/ms7721/OemCustomize.c
View File

@ -22,7 +22,6 @@
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)

1
src/mainboard/msi/ms7721/buildOpts.c
View File

@ -41,7 +41,6 @@
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE

2
src/mainboard/pcengines/apu1/buildOpts.c
View File

@ -26,8 +26,6 @@
*/
#include <stdlib.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */

2
src/mainboard/pcengines/apu2/BiosCallOuts.c
View File

@ -17,8 +17,6 @@
#include "amdlib.h"
#include <spd_bin.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Ids.h"
#include "OptionsIds.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "gpio_ftns.h"

1
src/mainboard/pcengines/apu2/OemCustomize.c
View File

@ -15,7 +15,6 @@
#include <northbridge/amd/pi/agesawrapper.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
{

1
src/mainboard/supermicro/h8qgi/BiosCallOuts.c
View File

@ -17,7 +17,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Ids.h"
#include <arch/io.h>
#ifdef __PRE_RAM__

2
src/mainboard/supermicro/h8qgi/buildOpts.c
View File

@ -17,8 +17,6 @@
#include "AGESA.h"
#include "AdvancedApi.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* AGESA will check the OEM configuration during preprocessing stage,
* coreboot enable -Wundef option, so we should make sure we have all contanstand defined

1
src/mainboard/supermicro/h8scm/BiosCallOuts.c
View File

@ -17,7 +17,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Ids.h"
#include <stdlib.h>
const BIOS_CALLOUT_STRUCT BiosCallouts[] =

2
src/mainboard/supermicro/h8scm/buildOpts.c
View File

@ -17,8 +17,6 @@
#include "AGESA.h"
#include "AdvancedApi.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
/* AGESA will check the OEM configuration during preprocessing stage,
* coreboot enable -Wundef option, so we should make sure we have all contanstand defined

1
src/mainboard/tyan/s8226/BiosCallOuts.c
View File

@ -17,7 +17,6 @@
#include "amdlib.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Ids.h"
#include <arch/io.h>
#include <stdlib.h>

2
src/mainboard/tyan/s8226/buildOpts.c
View File

@ -17,8 +17,6 @@
#include "AGESA.h"
#include "AdvancedApi.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* AGESA will check the OEM configuration during preprocessing stage,
* coreboot enable -Wundef option, so we should make sure we have all contanstand defined