vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01
The headers added are generated as per FSP v2422_01. Previous FSP version was v2374_01. Changes Include: - Add CnviDdrRfim UPD in FspmUpd.h - UPDs description update in FspmUpd.h BUG=b:205512463 BRANCH=None TEST=Build and boot brya Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Ronak Kanabar
Werner Zeh
parent
53075c720b
commit
a2610581a5
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@ -454,10 +454,10 @@ typedef struct {
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UINT8 ApertureSize;
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/** Offset 0x01D0 - Board Type
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MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC
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DDR5, 5=ULT/ULX/Mobile Halo Type3, 6=ULT/ULX/Mobile Halo Type4, 8=UP Server
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0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 2:Desktop 2DPC DDR5, 5:ULT/ULX/Mobile Halo
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Type3, 6:ULT/ULX/Mobile Halo Type4, 8:UP Server
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MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical,
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4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server
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0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical,
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4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server
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**/
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UINT8 UserBd;
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@ -474,7 +474,7 @@ typedef struct {
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/** Offset 0x01D4 - SA GV
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System Agent dynamic frequency support and when enabled memory will be training
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at three different frequencies.
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at four different frequencies.
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0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled
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**/
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UINT8 SaGv;
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@ -1966,9 +1966,11 @@ typedef struct {
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**/
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UINT8 PchHdaIDispCodecDisconnect;
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/** Offset 0x080D - Reserved
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/** Offset 0x080D - CNVi DDR RFI Mitigation
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Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
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$EN_DIS
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**/
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UINT8 Reserved27;
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UINT8 CnviDdrRfim;
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/** Offset 0x080E - Debug Interfaces
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Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
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@ -1991,7 +1993,7 @@ typedef struct {
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/** Offset 0x0811 - Reserved
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**/
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UINT8 Reserved28[3];
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UINT8 Reserved27[3];
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/** Offset 0x0814 - Serial Io Uart Debug BaudRate
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Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
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@ -2019,7 +2021,7 @@ typedef struct {
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/** Offset 0x081B - Reserved
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**/
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UINT8 Reserved29;
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UINT8 Reserved28;
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/** Offset 0x081C - Serial Io Uart Debug Mmio Base
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Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
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@ -2339,7 +2341,7 @@ typedef struct {
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/** Offset 0x0854 - Reserved
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**/
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UINT8 Reserved30;
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UINT8 Reserved29;
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/** Offset 0x0855 - Extern Therm Status
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Enables/Disable Extern Therm Status
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@ -2379,7 +2381,7 @@ typedef struct {
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/** Offset 0x085B - Reserved
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**/
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UINT8 Reserved31;
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UINT8 Reserved30;
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/** Offset 0x085C - Exit On Failure (MRC)
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Enables/Disable Exit On Failure (MRC)
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@ -2485,7 +2487,7 @@ typedef struct {
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/** Offset 0x086D - Reserved
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**/
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UINT8 Reserved32[2];
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UINT8 Reserved31[2];
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/** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
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Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
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@ -2544,7 +2546,7 @@ typedef struct {
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/** Offset 0x087E - Reserved
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**/
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UINT8 Reserved33;
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UINT8 Reserved32;
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/** Offset 0x087F - Idle Energy Mc0Ch0Dimm0
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Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
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@ -2754,7 +2756,7 @@ typedef struct {
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/** Offset 0x08A8 - Reserved
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**/
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UINT8 Reserved34[2];
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UINT8 Reserved33[2];
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/** Offset 0x08AA - Rapl Power Floor Ch0
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Power budget ,range[255;0],(0= 5.3W Def)
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@ -2786,7 +2788,7 @@ typedef struct {
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/** Offset 0x08AF - Reserved
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**/
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UINT8 Reserved35;
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UINT8 Reserved34;
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/** Offset 0x08B0 - User Manual Threshold
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Disabled: Predefined threshold will be used.\n
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@ -2860,7 +2862,7 @@ typedef struct {
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/** Offset 0x08BB - Reserved
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**/
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UINT8 Reserved36;
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UINT8 Reserved35;
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/** Offset 0x08BC - Post Code Output Port
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This option configures Post Code Output Port
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@ -2887,7 +2889,7 @@ typedef struct {
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/** Offset 0x08C1 - Reserved
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**/
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UINT8 Reserved37[3];
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UINT8 Reserved36[3];
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/** Offset 0x08C4 - BCLK RFI Frequency
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Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
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@ -2937,7 +2939,7 @@ typedef struct {
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/** Offset 0x08DB - Reserved
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**/
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UINT8 Reserved38[3];
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UINT8 Reserved37[3];
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/** Offset 0x08DE - REFRESH_PANIC_WM
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DEPRECATED
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@ -2963,7 +2965,7 @@ typedef struct {
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/** Offset 0x08E2 - Reserved
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**/
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UINT8 Reserved39[9];
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UINT8 Reserved38[9];
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/** Offset 0x08EB - Skip external display device scanning
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Enable: Do not scan for external display device, Disable (Default): Scan external
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@ -2986,7 +2988,7 @@ typedef struct {
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/** Offset 0x08EE - Reserved
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**/
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UINT8 Reserved40;
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UINT8 Reserved39;
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/** Offset 0x08EF - Panel Power Enable
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Control for enabling/disabling VDD force bit (Required only for early enabling of
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@ -3003,7 +3005,7 @@ typedef struct {
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/** Offset 0x08F1 - Reserved
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**/
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UINT8 Reserved41[3];
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UINT8 Reserved40[3];
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/** Offset 0x08F4 - PMR Size
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Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
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@ -3017,7 +3019,7 @@ typedef struct {
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/** Offset 0x08F9 - Reserved
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**/
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UINT8 Reserved42[95];
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UINT8 Reserved41[95];
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/** Offset 0x0958 - TotalFlashSize
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Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
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@ -3033,7 +3035,7 @@ typedef struct {
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/** Offset 0x095C - Reserved
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**/
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UINT8 Reserved43[12];
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UINT8 Reserved42[12];
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/** Offset 0x0968 - Smbus dynamic power gating
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Disable or Enable Smbus dynamic power gating.
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@ -3099,7 +3101,7 @@ typedef struct {
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/** Offset 0x0972 - Reserved
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**/
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UINT8 Reserved44[2];
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UINT8 Reserved43[2];
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/** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1
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Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
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@ -3136,7 +3138,7 @@ typedef struct {
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/** Offset 0x0A97 - Reserved
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**/
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UINT8 Reserved45;
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UINT8 Reserved44;
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/** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART used for debug
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@ -3162,7 +3164,7 @@ typedef struct {
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/** Offset 0x0AA8 - Reserved
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**/
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UINT8 Reserved46[104];
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UINT8 Reserved45[104];
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} FSP_M_CONFIG;
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/** Fsp M UPD Configuration
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