soc/amd/common/block/include: make include guards more uniform
TEST=Timeless build doesn't change for Mandolin and Gardenia. Change-Id: I5d3ae1459c333658f4c86388f1822d92ca13c658 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held
parent
33b92efa51
commit
a262fc6b07
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __CALLOUTS_AMD_AGESA_H__
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#define __CALLOUTS_AMD_AGESA_H__
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#ifndef __AMD_BLOCK_CALLOUTS_AGESA_H__
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#define __AMD_BLOCK_CALLOUTS_AGESA_H__
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#include <amdblocks/agesawrapper.h>
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#include <stdint.h>
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@ -69,4 +69,4 @@ typedef struct {
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extern const BIOS_CALLOUT_STRUCT BiosCallouts[];
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extern const int BiosCalloutsLen;
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#endif /* __CALLOUTS_AMD_AGESA_H__ */
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#endif /* __AMD_BLOCK_CALLOUTS_AGESA_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_ACPI_H__
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#define __AMDBLOCKS_ACPI_H__
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#ifndef __AMD_BLOCK_ACPI_H__
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#define __AMD_BLOCK_ACPI_H__
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#include <types.h>
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#include <soc/nvs.h>
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@ -44,4 +44,4 @@ void set_pm1cnt_s5(void);
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void acpi_enable_sci(void);
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void acpi_disable_sci(void);
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#endif /* __AMDBLOCKS_ACPI_H__ */
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#endif /* __AMD_BLOCK_ACPI_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __AMDBLOCKS_ACPIMMIO_H__
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#define __AMDBLOCKS_ACPIMMIO_H__
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#ifndef __AMD_BLOCK_ACPIMMIO_H__
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#define __AMD_BLOCK_ACPIMMIO_H__
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#include <device/mmio.h>
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#include <types.h>
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@ -508,4 +508,4 @@ static inline void aoac_write8(uint8_t reg, uint8_t value)
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write8(acpimmio_aoac + reg, value);
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}
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#endif /* __AMDBLOCKS_ACPIMMIO_H__ */
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#endif /* __AMD_BLOCK_ACPIMMIO_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __AMDBLOCKS_ACPIMMIO_MAP_H__
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#define __AMDBLOCKS_ACPIMMIO_MAP_H__
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#ifndef __AMD_BLOCK_ACPIMMIO_MAP_H__
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#define __AMD_BLOCK_ACPIMMIO_MAP_H__
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/*
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* The following AcpiMmio register block mapping represents definitions
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@ -132,4 +132,4 @@
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#endif
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#endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */
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#endif /* __AMD_BLOCK_ACPIMMIO_MAP_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AGESAWRAPPER_H__
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#define __AGESAWRAPPER_H__
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#ifndef __AMD_BLOCK_AGESAWRAPPER_H__
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#define __AMD_BLOCK_AGESAWRAPPER_H__
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#include <agesa_headers.h>
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@ -39,4 +39,4 @@ void SetNbMidParams(GNB_MID_CONFIGURATION *params);
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void set_board_env_params(GNB_ENV_CONFIGURATION *params);
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void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly);
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#endif /* __AGESAWRAPPER_H__ */
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#endif /* __AMD_BLOCK_AGESAWRAPPER_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AGESAWRAPPER_CALL_H__
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#define __AGESAWRAPPER_CALL_H__
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#ifndef __AMD_BLOCK_AGESAWRAPPER_CALL_H__
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#define __AMD_BLOCK_AGESAWRAPPER_CALL_H__
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#include <amdblocks/agesawrapper.h>
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#include <stdint.h>
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@ -41,4 +41,4 @@ static inline u32 do_agesawrapper(AGESA_STRUCT_NAME func, const char *name)
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return (u32)ret;
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}
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#endif /* __AGESAWRAPPER_CALL_H__ */
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#endif /* __AMD_BLOCK_AGESAWRAPPER_CALL_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_ALINK_H__
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#define __AMDBLOCKS_ALINK_H__
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#ifndef __AMD_BLOCK_ALINK_H__
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#define __AMD_BLOCK_ALINK_H__
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#include <stdint.h>
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@ -32,4 +32,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
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void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
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void alink_ax_indx(u32 space /* c or p? */, u32 axindc, u32 mask, u32 val);
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#endif /* __AMDBLOCKS_ALINK_H__ */
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#endif /* __AMD_BLOCK_ALINK_H__ */
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@ -1,8 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_PCI_MMCONF_H__
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#define __AMDBLOCKS_PCI_MMCONF_H__
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#ifndef __AMD_BLOCK_PCI_MMCONF_H__
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#define __AMD_BLOCK_PCI_MMCONF_H__
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void enable_pci_mmconf(void);
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#endif
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#endif /* __AMD_BLOCK_PCI_MMCONF_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMD_PCI_UTIL_H__
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#define __AMD_PCI_UTIL_H__
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#ifndef __AMD_BLOCK_PCI_UTIL_H__
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#define __AMD_BLOCK_PCI_UTIL_H__
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#include <stdint.h>
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#include <soc/amd_pci_int_defs.h>
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@ -31,4 +31,4 @@ void write_pci_cfg_irqs(void);
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void write_pci_int_table(void);
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const struct irq_idx_name *sb_get_apic_reg_association(size_t *size);
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#endif /* __AMD_PCI_UTIL_H__ */
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#endif /* __AMD_BLOCK_PCI_UTIL_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_BIOSRAM_H__
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#define __AMDBLOCKS_BIOSRAM_H__
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#ifndef __AMD_BLOCK_BIOSRAM_H__
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#define __AMD_BLOCK_BIOSRAM_H__
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#include <stdint.h>
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@ -26,4 +26,4 @@ uint32_t get_uma_size(void);
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/* Returns the saved UMA base */
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uint64_t get_uma_base(void);
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#endif
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#endif /* __AMD_BLOCK_BIOSRAM_H__ */
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@ -1,10 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMD_CAR_H__
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#define __AMD_CAR_H__
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#ifndef __AMD_BLOCK_CAR_H__
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#define __AMD_BLOCK_CAR_H__
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#include <stdint.h>
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void ap_teardown_car(uint32_t flags);
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#endif /* __AMD_CAR_H__ */
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#endif /* __AMD_BLOCK_CAR_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_CHIP_H__
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#define __AMDBLOCKS_CHIP_H__
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#ifndef __AMD_BLOCK_CHIP_H__
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#define __AMD_BLOCK_CHIP_H__
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#include <amdblocks/espi.h>
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#include <amdblocks/spi.h>
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@ -28,4 +28,4 @@ struct soc_amd_common_config {
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*/
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const struct soc_amd_common_config *soc_get_common_config(void);
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#endif
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#endif /* __AMD_BLOCK_CHIP_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __DIMMSPD_H__
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#define __DIMMSPD_H__
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#ifndef __AMD_BLOCK_DIMM_SPD_H__
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#define __AMD_BLOCK_DIMM_SPD_H__
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#include <amdblocks/agesawrapper.h>
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#include <stddef.h>
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@ -15,4 +15,4 @@
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int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len);
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int sb_read_spd(uint8_t spdAddress, char *buf, size_t len);
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#endif
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#endif /* __AMD_BLOCK_DIMM_SPD_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_ESPI_H__
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#define __AMDBLOCKS_ESPI_H__
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#ifndef __AMD_BLOCK_ESPI_H__
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#define __AMD_BLOCK_ESPI_H__
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#include <stdint.h>
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#include <stddef.h>
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@ -118,4 +118,4 @@ void espi_update_static_bar(uintptr_t bar);
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*/
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int espi_setup(void);
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#endif /* __AMDBLOCKS_ESPI_H__ */
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#endif /* __AMD_BLOCK_ESPI_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCK_GPIO_BANKS_H__
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#define __AMDBLOCK_GPIO_BANKS_H__
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#ifndef __AMD_BLOCK_GPIO_BANKS_H__
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#define __AMD_BLOCK_GPIO_BANKS_H__
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#include <types.h>
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@ -361,4 +361,4 @@ void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items)
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/* May be implemented by soc to handle special cases */
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void soc_gpio_hook(uint8_t gpio, uint8_t mux);
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#endif /* __AMDBLOCK_GPIO_BANKS_H__ */
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#endif /* __AMD_BLOCK_GPIO_BANKS_H__ */
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@ -1,11 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_HDA_H__
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#define __AMDBLOCKS_HDA_H__
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#ifndef __AMD_BLOCK_HDA_H__
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#define __AMD_BLOCK_HDA_H__
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#include <device/device.h>
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/* SoC callback to add any quirks to HDA device node in SSDT. */
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void hda_soc_ssdt_quirks(const struct device *dev);
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#endif /* __AMDBLOCKS_HDA_H__ */
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#endif /* __AMD_BLOCK_HDA_H__ */
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@ -1,11 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMD_IMAGE_H__
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#define __AMD_IMAGE_H__
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#ifndef __AMD_BLOCK_IMAGE_H__
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#define __AMD_BLOCK_IMAGE_H__
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#include <stdint.h>
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void *amd_find_image(const void *start_address, const void *end_address,
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uint32_t alignment, const char name[8]);
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#endif /* __AMD_IMAGE_H__ */
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#endif /* __AMD_BLOCK_IMAGE_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_LPC_H__
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#define __AMDBLOCKS_LPC_H__
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#ifndef __AMD_BLOCK_LPC_H__
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#define __AMD_BLOCK_LPC_H__
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#include <types.h>
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@ -198,4 +198,4 @@ void lpc_set_spibase(uint32_t base);
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/* Enable SPI ROM (SPI_ROM_ENABLE, SPI_ROM_ALT_ENABLE) */
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void lpc_enable_spi_rom(uint32_t enable);
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#endif /* __AMDBLOCKS_LPC_H__ */
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#endif /* __AMD_BLOCK_LPC_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMD_PSP_H__
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#define __AMD_PSP_H__
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#ifndef __AMD_BLOCK_PSP_H__
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#define __AMD_BLOCK_PSP_H__
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/* Get the mailbox base address - specific to family of device. */
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void *soc_get_mbox_address(void);
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@ -74,4 +74,4 @@ void psp_notify_sx_info(u8 sleep_type);
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int psp_load_named_blob(enum psp_blob_type type, const char *name);
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#endif /* __AMD_PSP_H__ */
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#endif /* __AMD_BLOCK_PSP_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMD_RESET_H__
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#define __AMD_RESET_H__
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#ifndef __AMD_BLOCK_RESET_H__
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#define __AMD_BLOCK_RESET_H__
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#include <console/console.h>
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#include <arch/cache.h>
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@ -26,4 +26,4 @@ static inline __noreturn void cold_reset(void)
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halt();
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}
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#endif /* __AMD_RESET_H__ */
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#endif /* __AMD_BLOCK_RESET_H__ */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMD_S3_RESUME_H__
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#define __AMD_S3_RESUME_H__
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#ifndef __AMD_BLOCK_S3_RESUME_H__
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#define __AMD_BLOCK_S3_RESUME_H__
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#include <agesa_headers.h>
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@ -9,4 +9,4 @@ AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock);
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AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock);
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AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock);
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#endif /* __AMD_S3_RESUME_H__ */
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#endif /* __AMD_BLOCK_S3_RESUME_H__ */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_SATA_H__
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#define __AMDBLOCKS_SATA_H__
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#ifndef __AMD_BLOCK_SATA_H__
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#define __AMD_BLOCK_SATA_H__
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#include <device/device.h>
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void soc_enable_sata_features(struct device *dev);
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#endif /* __AMDBLOCKS_SATA_H__ */
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#endif /* __AMD_BLOCK_SATA_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __AMDBLOCKS_SPI_H__
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#define __AMDBLOCKS_SPI_H__
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#ifndef __AMD_BLOCK_SPI_H__
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#define __AMD_BLOCK_SPI_H__
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#include <types.h>
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@ -108,4 +108,4 @@ void spi_write8(uint8_t reg, uint8_t val);
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void spi_write16(uint8_t reg, uint16_t val);
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void spi_write32(uint8_t reg, uint32_t val);
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#endif /* __AMDBLOCKS_SPI_H__ */
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#endif /* __AMD_BLOCK_SPI_H__ */
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