soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress
This patch creates a helper function to check if any SPI transaction is pending. As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation, it's important to ensure there is no pending SPI transaction before setting SPI lock bits. BUG=b:211954778 TEST=Able to build google/brya with this patch and no error msg seen due to `SPI transaction is pending`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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@ -161,6 +161,18 @@ static int exec_sync_hwseq_xfer(struct fast_spi_flash_ctx *ctx,
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return wait_for_hwseq_xfer(ctx, flash_addr);
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}
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int fast_spi_cycle_in_progress(void)
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{
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BOILERPLATE_CREATE_CTX(ctx);
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int ret = wait_for_hwseq_spi_cycle_complete(ctx);
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if (ret != SUCCESS)
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printk(BIOS_ERR, "SPI Transaction Timeout (Exceeded %d ms) due to prior"
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" operation is pending\n", SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
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return ret;
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}
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/*
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* Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
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* that the operation does not cross page boundary.
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@ -5,6 +5,8 @@
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#include <types.h>
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/* Check if SPI transaction is pending */
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int fast_spi_cycle_in_progress(void);
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/*
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* Disable the BIOS write protect and Enable Prefetching and Caching.
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*/
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