add support for ICH4. more i955pm stuff.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/digitallogic/adl855pc/Config.lb

@@ -140,7 +140,7 @@ end
 
 makerule ./failover.inc
 	depends "./failover.E ./romcc"
-	action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
+	action "./romcc -O -mcpu=p4 -o failover.inc --label-prefix=failover ./failover.E"
 end
 
 makerule ./auto.E 
@@ -149,7 +149,7 @@ makerule ./auto.E
 end
 makerule ./auto.inc 
 	depends "./auto.E ./romcc"
-	action	"./romcc   -O -mcpu=c3 ./auto.E "
+	action	"./romcc   -O -mcpu=p4 ./auto.E "
 end
 
 ##

src/mainboard/digitallogic/adl855pc/auto.c

@@ -5,7 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/smp/lapic.h>
-#include "option_table.h"
+//#include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"

src/northbridge/intel/i855pm/raminit.c

@@ -5,7 +5,7 @@
 /* converted to C 6/2004 yhlu */
 
 #define DEBUG_RAM_CONFIG 1
-
+#define ASM_CONSOLE_LOGLEVEL 10
 #define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 0)) 
 
 /* DDR DIMM Mode register Definitions */
@@ -1512,7 +1512,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
                                 dimm_mask |= (1 << i);
                         }
                 }
-#if 1
+#if 0
                 device = ctrl->channel1[i];
                 if (device) {
                         byte = spd_read_byte(ctrl->channel1[i], 2);
@@ -1798,12 +1798,13 @@ static void dram_finish(const struct mem_controller *ctrl)
 #endif
 
 		/* Clear the ECC error bits */
+#if 0
 		pci_write_config8(ctrl->d0f1, 0x80, 0x03); /* dev 0, function 1, offset 80 */
 		pci_write_config8(ctrl->d0f1, 0x82, 0x03); /* dev 0, function 1, offset 82 */
 
 		pci_write_config32(ctrl->d0f1, 0x40, 1<<18); /* clear dev 0, function 1, offset 40; bit 18 by writing a 1 to it */
   	        pci_write_config32(ctrl->d0f1, 0x44, 1<<18); /* clear dev 0, function 1, offset 44; bit 18 by writing a 1 to it */
-
+#endif
 		pci_write_config8(ctrl->d0, 0x52, 0x0d);
 	}
 	

targets/digitallogic/adl855pc/Config.lb

@@ -90,7 +90,8 @@ romimage "normal"
 	mainboard digitallogic/adl855pc
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
-	payload ../../../../../lnxieepro100.ebi
+#	payload ../../../../../lnxieepro100.ebi
+	payload /etc/hosts
 end
 
 romimage "fallback" 
@@ -100,7 +101,8 @@ romimage "fallback"
 	mainboard digitallogic/adl855pc
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
-	payload ../../../../../lnxieepro100.ebi
+#	payload ../../../../../lnxieepro100.ebi
+	payload /etc/hosts
 end
 
 buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

util/flash_and_burn/flash_enable.c

@@ -82,6 +82,31 @@ static int enable_flash_e7500(struct pci_dev *dev, char *name)
 	return 0;
 }
 
+static int enable_flash_ich4(struct pci_dev *dev, char *name)
+{
+	/* register 4e.b gets or'ed with one */
+	unsigned char old, new;
+	/* if it fails, it fails. There are so many variations of broken mobos
+	 * that it is hard to argue that we should quit at this point. 
+	 */
+
+	old = pci_read_byte(dev, 0x4e);
+
+	new = old | 1;
+
+	if (new == old)
+		return 0;
+
+	pci_write_byte(dev, 0x4e, new);
+
+	if (pci_read_byte(dev, 0x4e) != new) {
+		printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
+		       0x4e, new, name);
+		return -1;
+	}
+	return 0;
+}
+
 static int enable_flash_vt8235(struct pci_dev *dev, char *name)
 {
 	unsigned char old, new, val;
@@ -234,6 +259,7 @@ typedef struct penable {
 static FLASH_ENABLE enables[] = {
 	{0x1039, 0x0630, "sis630", enable_flash_sis630},
 	{0x8086, 0x2480, "E7500", enable_flash_e7500},
+	{0x8086, 0x24c0, "ICH4", enable_flash_ich4},
 	{0x1106, 0x8231, "VT8231", enable_flash_vt8231},
 	{0x1106, 0x3177, "VT8235", enable_flash_vt8235},
 	{0x1078, 0x0100, "CS5530", enable_flash_cs5530},