sb/amd/cs5536: Remove includes of C files

The romstage for CS5536 platforms were including early_smbus.c and
early_setup.c.  Build these into romstage from the makefile, and remove
the #includes.

Add a Kconfig option for platforms that do not use the
early smbus code.

Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/aaeon/pfm-540i_revb/romstage.c

@@ -28,8 +28,6 @@
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <superio/smsc/smscsuperio/smscsuperio.h>
 #include <northbridge/amd/lx/raminit.h>
 

src/mainboard/amd/db800/romstage.c

@@ -25,8 +25,6 @@
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/amd/f2950/romstage.c

@@ -25,8 +25,6 @@
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/amd/norwich/romstage.c

@@ -25,8 +25,6 @@
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <northbridge/amd/lx/raminit.h>
 
 int spd_read_byte(unsigned int device, unsigned int address)

src/mainboard/amd/rumba/romstage.c

@@ -22,8 +22,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/gx2def.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
+#include <southbridge/amd/cs5536/cs5536.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

src/mainboard/artecgroup/dbe61/romstage.c

@@ -26,8 +26,6 @@
 #include <southbridge/amd/cs5536/cs5536.h>
 #include "spd_table.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <northbridge/amd/lx/raminit.h>
 
 int spd_read_byte(unsigned int device, unsigned int address)

src/mainboard/bachmann/ot200/romstage.c

@@ -27,8 +27,6 @@
 #include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <northbridge/amd/lx/raminit.h>
 
 int spd_read_byte(unsigned int device, unsigned int address)

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -23,8 +23,6 @@
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/iei/pcisa-lx-800-r10/romstage.c

@@ -26,8 +26,6 @@
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/iei/pm-lx-800-r11/romstage.c

@@ -25,8 +25,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
-#include <southbridge/amd/cs5536/early_smbus.c>
-#include <southbridge/amd/cs5536/early_setup.c>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/iei/pm-lx2-800-r10/romstage.c

@@ -27,8 +27,6 @@
 #include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
-#include <southbridge/amd/cs5536/early_smbus.c>
-#include <southbridge/amd/cs5536/early_setup.c>
 #include <superio/smsc/smscsuperio/smscsuperio.h>
 #include <northbridge/amd/lx/raminit.h>
 

src/mainboard/lippert/hurricane-lx/romstage.c

@@ -27,9 +27,8 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
+#include <southbridge/amd/cs5536/smbus.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/lippert/literunner-lx/romstage.c

@@ -28,8 +28,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
+#include <southbridge/amd/cs5536/smbus.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/lippert/roadrunner-lx/romstage.c

@@ -28,8 +28,6 @@
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -28,8 +28,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
+#include <southbridge/amd/cs5536/smbus.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/pcengines/alix1c/Kconfig

@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select POWER_BUTTON_DEFAULT_DISABLE
 	select HAVE_OPTION_TABLE
 	select HAVE_CMOS_DEFAULT
+	select NO_EARLY_SMBUS
 
 config MAINBOARD_DIR
 	string

src/mainboard/pcengines/alix1c/romstage.c

@@ -30,10 +30,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-/* The ALIX1.C has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void) { }
-
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 

src/mainboard/pcengines/alix2d/Kconfig

@@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
 	select POWER_BUTTON_FORCE_DISABLE
+	select NO_EARLY_SMBUS
 
 config MAINBOARD_DIR
 	string

src/mainboard/pcengines/alix2d/romstage.c

@@ -30,11 +30,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-/* The ALIX.2D has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void) { }
-
-#include "southbridge/amd/cs5536/early_setup.c"
-
 /* The part is a Hynix hy5du121622ctp-d43.
  *
  * HY 5D U 12 16 2 2 C <blank> T <blank> P D43

src/mainboard/traverse/geos/romstage.c

@@ -26,8 +26,6 @@
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <northbridge/amd/lx/raminit.h>
 
 int spd_read_byte(unsigned int device, unsigned int address)

src/mainboard/winent/pl6064/romstage.c

@@ -27,8 +27,6 @@
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <northbridge/amd/lx/raminit.h>

src/mainboard/wyse/s50/romstage.c

@@ -24,8 +24,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/gx2def.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
+#include <southbridge/amd/cs5536/cs5536.h>
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {

src/southbridge/amd/cs5536/Kconfig

@@ -16,3 +16,12 @@
 config SOUTHBRIDGE_AMD_CS5536
 	bool
 	select UDELAY_TSC
+
+if SOUTHBRIDGE_AMD_CS5536
+
+config NO_EARLY_SMBUS
+	def_bool n
+	help
+	  Skip the CS5536 early SMBUS initialization.
+
+endif

src/southbridge/amd/cs5536/Makefile.inc

@@ -15,6 +15,9 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
 
+romstage-y += early_smbus.c
+romstage-y += early_setup.c
+
 ramstage-y += cs5536.c
 ramstage-y += ide.c
 ramstage-y += pirq.c

src/southbridge/amd/cs5536/cs5536.h

@@ -442,6 +442,10 @@
 #if defined(__PRE_RAM__)
 void cs5536_setup_onchipuart(int uart);
 void cs5536_disable_internal_uart(void);
+void cs5536_early_setup(void);
+
+void cs5536_enable_smbus(void);
+int smbus_read_byte(unsigned device, unsigned address);
 #else
 void chipsetinit(void);
 #endif

src/southbridge/amd/cs5536/early_setup.c

@@ -19,6 +19,12 @@
  *	AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide.
  */
 
+#include <arch/io.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/lxdef.h>
+#include "cs5536.h"
+
 /**
  * @brief Setup PCI IDSEL for CS5536
  */
@@ -244,7 +250,7 @@ void cs5536_setup_onchipuart(int uart)
  * and we don't want to hang on serial, so they are
  * commented out
  */
-static void cs5536_early_setup(void)
+void cs5536_early_setup(void)
 {
 	msr_t msr;
 

src/southbridge/amd/cs5536/early_smbus.c

@@ -13,13 +13,17 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/io.h>
 #include "cs5536.h"
 #include "smbus.h"
 
 /* initialization for SMBus Controller */
-static void cs5536_enable_smbus(void)
+void cs5536_enable_smbus(void)
 {
 
+	if (IS_ENABLED(CONFIG_NO_EARLY_SMBUS))
+		return;
+
 	/* Set SCL freq and enable SMB controller */
 	/*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */
 	outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2);
@@ -29,7 +33,7 @@ static void cs5536_enable_smbus(void)
 
 }
 
-static inline int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned device, unsigned address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }