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soc/intel/apollolake: provide gpio _HIGH/_LOW macros 

Internally, apollolake routes its interrupts as active high.
This includes SCI, SMI, and ACPI. Therefore, provide helper
macros such that the user can describe an interrupt's active
high/low polarity more easily. It helps for readability when
one is comparing gpio configuration next to APIC configuration
in different files. Additionally, the gpio APIC macros always
use a LEVEL trigger in order to let the APIC handle the
filtering of the IRQ on its own end.

BUG=chrome-os-partner:54977

Change-Id: Id8fdcd98f0920936cd2b1a687fd8fa07bce9a614
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15644
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
This commit is contained in:
Aaron Durbin 2016-07-12 16:46:20 -05:00
parent d41a338d55
commit a277bacd56
1 changed files with 23 additions and 0 deletions
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23
src/soc/intel/apollolake/include/soc/gpio.h
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@ -67,18 +67,41 @@ typedef uint32_t gpio_t;
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull)) PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull))
/*
* The following APIC macros assume the APIC will handle the filtering
* on its own end. One just needs to pass an active high message into the
* ITSS.
*/
#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
/* General purpose input, routed to SMI */ /* General purpose input, routed to SMI */
#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
_PAD_CFG_STRUCT(pad, \ _PAD_CFG_STRUCT(pad, \
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull)) PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull))
#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
/* General purpose input, routed to SCI */ /* General purpose input, routed to SCI */
#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
_PAD_CFG_STRUCT(pad, \ _PAD_CFG_STRUCT(pad, \
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull)) PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull))
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
/* General purpose input, routed to NMI */ /* General purpose input, routed to NMI */
#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
_PAD_CFG_STRUCT(pad, \ _PAD_CFG_STRUCT(pad, \