soc/amd/sabrina/include/aoac_defs: add additional UARTs

Compared to Cezanne there are 3 more UARTs controllers.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id98767197a21cb1a61f54fc9b256b10a9506c791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2022-01-11 16:43:46 +01:00
parent 1f0eb6b0db
commit a27d1fa175
1 changed files with 3 additions and 2 deletions

View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* TODO: Check if this is still correct */
#ifndef AMD_SABRINA_AOAC_DEFS_H #ifndef AMD_SABRINA_AOAC_DEFS_H
#define AMD_SABRINA_AOAC_DEFS_H #define AMD_SABRINA_AOAC_DEFS_H
@ -15,7 +13,10 @@
#define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_I2C5 10
#define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART0 11
#define FCH_AOAC_DEV_UART1 12 #define FCH_AOAC_DEV_UART1 12
#define FCH_AOAC_DEV_UART2 16
#define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_UART4 20
#define FCH_AOAC_DEV_UART3 26
#define FCH_AOAC_DEV_ESPI 27 #define FCH_AOAC_DEV_ESPI 27
#define FCH_AOAC_DEV_EMMC 28 #define FCH_AOAC_DEV_EMMC 28