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intel model_106cx: Include CAR from socket directory 

Since the socket layer is implemented with this CPU model, there
could potentially be multiple CPU models included.  There can be
only one cache_as_ram include, so select it directly within
the socket directory.

Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15757
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-07-20 08:50:38 +03:00
parent 81527e8d7f
commit a27fba67a0
3 changed files with 6 additions and 2 deletions
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2
src/cpu/intel/model_106cx/Makefile.inc
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@ -1,6 +1,4 @@
ramstage-y += model_106cx_init.c ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin

3
src/cpu/intel/socket_441/Makefile.inc
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@ -7,3 +7,6 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c

3
src/cpu/intel/socket_FCBGA559/Makefile.inc
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@ -6,3 +6,6 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c