GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/cyan: Switch eMMC and SD from ACPI to PCI mode 

Braswell boards don't work well with the eMMC and SD controller
in ACPI in payloads other than depthcharge - SeaBIOS requires
an onerous workaround (manually determining the PCI BAR0 address
for each eMMC and SD controller, then adding adding etc/sdcard
entries to the CBFS), and Tianocore can't see the devices at all.
To make the common use-case work better, switch to PCI mode.

Test: build/boot cyan variants with SeaBIOS and Tianocore
payloads, verify eMMC and SD card visible and bootable to
both payloads and OSes.

Change-Id: I71947603e22a37fe2c8ef4eaac8a3aa0d0ed1cec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40002
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2018-01-21 18:32:07 -06:00
parent 8fbfcc3a06
commit a2804781fe
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/google/cyan/devicetree.cb
View File

@ -19,7 +19,7 @@ chip soc/intel/braswell
# Set the parameters for SiliconInit
############################################################
register "PcdSdcardMode" = "PCH_ACPI_MODE"
register "PcdSdcardMode" = "PCH_PCI_MODE"
register "PcdEnableHsuart0" = "0"
register "PcdEnableHsuart1" = "1"
register "PcdEnableAzalia" = "1"
@ -36,7 +36,7 @@ chip soc/intel/braswell
register "PcdEnableI2C6" = "0"
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
register "PcdEmmcMode" = "PCH_ACPI_MODE"
register "PcdEmmcMode" = "PCH_PCI_MODE"
register "PcdUsb3ClkSsc" = "1"
register "PcdDispClkSsc" = "1"
register "PcdSataClkSsc" = "1"
@ -84,10 +84,10 @@ chip soc/intel/braswell
# LPE audio codec settings
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
# Enable devices in ACPI mode
# Enable LPSS and LPE devices in ACPI mode
register "lpss_acpi_mode" = "1"
register "emmc_acpi_mode" = "1"
register "sd_acpi_mode" = "1"
register "emmc_acpi_mode" = "0"
register "sd_acpi_mode" = "0"
register "lpe_acpi_mode" = "1"
# Disable SLP_X stretching after SUS power well fail.