diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 5266e8a78c..0bb6f40716 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -39,6 +39,7 @@ config SOC_AMD_PICASSO
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
 	select SOC_AMD_COMMON_BLOCK_EMMC
 	select SOC_AMD_COMMON_BLOCK_EMMC_SKIP_POWEROFF
+	select SOC_AMD_COMMON_BLOCK_GPP_CLK
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
 	select SOC_AMD_COMMON_BLOCK_HDA
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c
index efa008d6bb..8952c168d2 100644
--- a/src/soc/amd/picasso/fch.c
+++ b/src/soc/amd/picasso/fch.c
@@ -176,44 +176,7 @@ static void al2ahb_clock_gate(void)
 static void gpp_clk_setup(void)
 {
 	struct soc_amd_picasso_config *cfg = config_of_soc();
-
-	/* look-up table to be able to iterate over the PCIe clock output settings */
-	const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
-		GPP_CLK0_REQ_SHIFT,
-		GPP_CLK1_REQ_SHIFT,
-		GPP_CLK2_REQ_SHIFT,
-		GPP_CLK3_REQ_SHIFT,
-		GPP_CLK4_REQ_SHIFT,
-		GPP_CLK5_REQ_SHIFT,
-		GPP_CLK6_REQ_SHIFT,
-	};
-
-	uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
-
-	pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
-					    ARRAY_SIZE(cfg->gpp_clk_config));
-	for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
-		gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
-		/*
-		 * The remapping of values is done so that the default of the enum used for the
-		 * devicetree settings is the clock being enabled, so that a missing devicetree
-		 * configuration for this will result in an always active clock and not an
-		 * inactive PCIe clock output.
-		 */
-		switch (cfg->gpp_clk_config[i]) {
-		case GPP_CLK_REQ:
-			gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
-			break;
-		case GPP_CLK_OFF:
-			gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);
-			break;
-		case GPP_CLK_ON:
-		default:
-			gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]);
-		}
-	}
-
-	misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
+	gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config));
 }
 
 void fch_init(void *chip_info)
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 31f3ed689c..6c1eda5d5c 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -72,21 +72,6 @@
 #define GPE0_LIMIT			32
 #define TOTAL_BITS(a)			(8 * sizeof(a))
 
-/* FCH MISC Registers 0xfed80e00 */
-#define GPP_CLK_CNTRL			0x00
-#define   GPP_CLK0_REQ_SHIFT		0
-#define   GPP_CLK1_REQ_SHIFT		2
-#define   GPP_CLK4_REQ_SHIFT		4
-#define   GPP_CLK2_REQ_SHIFT		6
-#define   GPP_CLK3_REQ_SHIFT		8
-#define   GPP_CLK5_REQ_SHIFT		10
-#define   GPP_CLK6_REQ_SHIFT		12
-#define     GPP_CLK_OUTPUT_COUNT	7
-#define   GPP_CLK_REQ_MASK(clk_shift)	(0x3 << (clk_shift))
-#define   GPP_CLK_REQ_ON(clk_shift)	(0x3 << (clk_shift))
-#define   GPP_CLK_REQ_EXT(clk_shift)	(0x1 << (clk_shift))
-#define   GPP_CLK_REQ_OFF(clk_shift)	(0x0 << (clk_shift))
-
 #define MISC_CGPLL_CONFIG1		0x08
 #define   CG1PLL_SPREAD_SPECTRUM_ENABLE	BIT(0)
 #define MISC_CLK_CNTL1			0x40