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imgtec/pistachio: DDR row/bank/column mapping 

The DRAM configuration register, apart from holding the
device density and width also has a rudimentary address
mapping scheme. Currently this is set to the default
Bank/Row/Column. This means that the memory is segmented
into 8 chunks, each with a page detector. If all the
activity is in one section of memory then the other 7
page detectors could be idle.
Changing this to Row/Bank/Column would concatenate the
page detectors meaning that all 8 could be used by a
single initiator. This may not gain anything in a
synthetic bandwidth test but could yield extra performance
in a real world application or benchmark.

BRANCH=none
BUG=chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
     properly; all access to DDR works properly in
     Coreboot ramstage, Depthcharge and Linux;
     no performance tests were ran so far.

Change-Id: I22d86bf3b679ed63884d7436d9d7bbaf1726f640
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e852ed42afcdc2062a0037144bab723227cb1f1f
Original-Change-Id: If90b0cf5ce86db5e3d6d362873d22d4269e3a49f
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/264340
Original-Reviewed-by: James Hartley <james.hartley@imgtec.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9916
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ionela Voinescu 2015-03-30 11:59:10 +01:00 committed by Patrick Georgi
parent d1a21d7d71
commit a2c4f9ee9f
1 changed files with 2 additions and 2 deletions
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4
src/soc/imgtec/pistachio/ddr2_init.c
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@ -510,10 +510,10 @@ int init_ddr2(void)
* 5:2 Density 2Gb = 5 * 5:2 Density 2Gb = 5
* 6 Dram Type (MDDR/LPDDR2) Only 0 * 6 Dram Type (MDDR/LPDDR2) Only 0
* 7 Reserved 0 * 7 Reserved 0
* 10:8 Address Map R/B/C = 0 * 10:8 Address Map R/B/C = 1
* 31:11 Reserved * 31:11 Reserved
*/ */
write32(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000016); write32(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116);
/* PCFG_0 : Port 0 AXI config */ /* PCFG_0 : Port 0 AXI config */
if (BL8) if (BL8)
write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0);