diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c
index a167d2b58e..5460486709 100644
--- a/src/soc/mediatek/mt8183/auxadc.c
+++ b/src/soc/mediatek/mt8183/auxadc.c
@@ -18,11 +18,37 @@
 #include <delay.h>
 #include <soc/addressmap.h>
 #include <soc/auxadc.h>
+#include <soc/efuse.h>
 #include <soc/infracfg.h>
 #include <timer.h>
 
 static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE;
 
+#define ADC_GE_A_SHIFT		10
+#define ADC_GE_A_MASK		(0x3ff << ADC_GE_A_SHIFT)
+#define ADC_OE_A_SHIFT		0
+#define ADC_OE_A_MASK		(0x3ff << ADC_OE_A_SHIFT)
+#define ADC_CALI_EN_A_SHIFT	20
+#define ADC_CALI_EN_A_MASK	(0x1 << ADC_CALI_EN_A_SHIFT)
+
+static int cali_oe;
+static int cali_ge;
+static int calibrated = 0;
+static void mt_auxadc_update_cali(void)
+{
+	uint32_t cali_reg;
+	int cali_ge_a;
+	int cali_oe_a;
+
+	cali_reg = read32(&mtk_efuse->adc_cali_reg);
+
+	if ((cali_reg & ADC_CALI_EN_A_MASK) != 0) {
+		cali_oe_a = (cali_reg & ADC_OE_A_MASK) >> ADC_OE_A_SHIFT;
+		cali_ge_a = (cali_reg & ADC_GE_A_MASK) >> ADC_GE_A_SHIFT;
+		cali_ge = cali_ge_a - 512;
+		cali_oe = cali_oe_a - 512;
+	}
+}
 static uint32_t auxadc_get_rawdata(int channel)
 {
 	setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10);
@@ -44,8 +70,17 @@ static uint32_t auxadc_get_rawdata(int channel)
 
 int auxadc_get_voltage(unsigned int channel)
 {
+	uint32_t raw_value;
 	assert(channel < 16);
 
+	if (!calibrated) {
+		mt_auxadc_update_cali();
+		calibrated = 1;
+	}
+
 	/* 1.5V in 4096 steps */
-	return (int)((int64_t)auxadc_get_rawdata(channel) * 1500000 / 4096);
+	raw_value = auxadc_get_rawdata(channel);
+
+	raw_value = raw_value - cali_oe;
+	return (int)((int64_t)raw_value * 1500000 / (4096 + cali_ge));
 }
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index d41b2b942e..e9f80d1607 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -50,6 +50,7 @@ enum {
 	IOCFG_LB_BASE		= IO_PHYS + 0x01E70000,
 	IOCFG_LM_BASE		= IO_PHYS + 0x01E80000,
 	IOCFG_BL_BASE		= IO_PHYS + 0x01E90000,
+	EFUSEC_BASE		= IO_PHYS + 0x01F10000,
 	IOCFG_LT_BASE		= IO_PHYS + 0x01F20000,
 	IOCFG_TL_BASE		= IO_PHYS + 0x01F30000,
 	SSUSB_SIF_BASE		= IO_PHYS + 0x01F40300,
diff --git a/src/soc/mediatek/mt8183/include/soc/efuse.h b/src/soc/mediatek/mt8183/include/soc/efuse.h
new file mode 100644
index 0000000000..32126abc4e
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/efuse.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MTK_EFUSE_H
+#define _MTK_EFUSE_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct efuse_regs {
+	uint32_t rserved[109];
+	uint32_t adc_cali_reg;
+};
+
+check_member(efuse_regs, adc_cali_reg, 0x1b4);
+static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE;
+
+#endif