include/console: Align ramstage Boot State Machine postcodes
This patch ensures all boot state machine postcodes are in right order. Move POST_ENTRY_RAMSTAGE macro definition after POST_BS_PAYLOAD_BOOT. Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -181,14 +181,6 @@
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*/
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#define POST_PRE_HARDWAREMAIN 0x79
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/**
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* \brief Entry into coreboot in RAM stage main()
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*
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* This is the first call in hardwaremain.c. If this code is POSTed, then
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* ramstage has successfully loaded and started executing.
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*/
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#define POST_ENTRY_RAMSTAGE 0x80
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/**
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* \brief Load Payload
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*
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@ -203,6 +195,14 @@
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*/
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#define POST_BS_PAYLOAD_BOOT 0x7b
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/**
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* \brief Entry into coreboot in RAM stage main()
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*
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* This is the first call in hardwaremain.c. If this code is POSTed, then
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* ramstage has successfully loaded and started executing.
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*/
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#define POST_ENTRY_RAMSTAGE 0x80
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/**
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* \brief Before calling FSP Notify before End of Firmware
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*
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