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include/console: Align ramstage Boot State Machine postcodes 

This patch ensures all boot state machine postcodes are in right
order. Move POST_ENTRY_RAMSTAGE macro definition after
POST_BS_PAYLOAD_BOOT.

Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2021-05-04 23:36:36 +05:30 committed by Patrick Georgi
parent 88a0ce6e11
commit a2cf34129f
1 changed files with 8 additions and 8 deletions
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16
src/include/console/post_codes.h
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@ -181,14 +181,6 @@
*/
#define POST_PRE_HARDWAREMAIN 0x79
/**
* \brief Entry into coreboot in RAM stage main()
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
* ramstage has successfully loaded and started executing.
*/
#define POST_ENTRY_RAMSTAGE 0x80
/**
* \brief Load Payload
*
@ -203,6 +195,14 @@
*/
#define POST_BS_PAYLOAD_BOOT 0x7b
/**
* \brief Entry into coreboot in RAM stage main()
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
* ramstage has successfully loaded and started executing.
*/
#define POST_ENTRY_RAMSTAGE 0x80
/**
* \brief Before calling FSP Notify before End of Firmware
*