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lynxpoint: Fix LP clock gating setup for LPC 

This bit offset is incorrect and should only be set based
on another bit in a different register.

Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2973
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Duncan Laurie 2013-03-22 11:24:45 -07:00 committed by Ronald G. Minnich
parent 0ce2b43682
commit a2d6a40480
1 changed files with 4 additions and 1 deletions
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5
src/southbridge/intel/lynxpoint/lpc.c
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@ -458,7 +458,10 @@ static void enable_lp_clock_gating(device_t dev)
RCBA32_OR(0x900, 0x0000031f); RCBA32_OR(0x900, 0x0000031f);
reg32 = RCBA32(CG); reg32 = RCBA32(CG);
reg32 |= (1 << 31); // LPC Dynamic if (RCBA32(0x3454) & (1 << 4))
reg32 &= ~(1 << 29); // LPC Dynamic
else
reg32 |= (1 << 29); // LPC Dynamic
reg32 |= (1 << 30); // LP LPC reg32 |= (1 << 30); // LP LPC
reg32 |= (1 << 28); // GPIO Dynamic reg32 |= (1 << 28); // GPIO Dynamic
reg32 |= (1 << 27); // HPET Dynamic reg32 |= (1 << 27); // HPET Dynamic