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northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devices 

When an Extended Temperature Range DIMM is installed on a channel
the refresh rate should be increased per the BKDG recommendations
to allow correct operation at higher temperature ranges.

Set fast refresh on a channel if an ETR DIMM is installed on that
channel.

Change-Id: I7a085d34efc78f3f0794a5cb33b88f27a5e6d54e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13144
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Timothy Pearson 2015-11-24 14:11:50 -06:00 committed by Martin Roth
parent ba2af2e21d
commit a2df081d44
2 changed files with 14 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@ -3993,6 +3993,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
u32 DramTimingLo, DramTimingHi; u32 DramTimingLo, DramTimingHi;
u8 tCK16x; u8 tCK16x;
u16 Twtr; u16 Twtr;
uint8_t Etr[2];
u8 LDIMM; u8 LDIMM;
u8 MTB16x; u8 MTB16x;
u8 byte; u8 byte;
@ -4011,6 +4012,8 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
Trc = 0; Trc = 0;
Twr = 0; Twr = 0;
Twtr = 0; Twtr = 0;
for (i=0; i < 2; i++)
Etr[i] = 0;
for (i=0; i < 4; i++) for (i=0; i < 4; i++)
Trfc[i] = 0; Trfc[i] = 0;
Tfaw = 0; Tfaw = 0;
@ -4077,6 +4080,10 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
val *= MTB16x; val *= MTB16x;
if (Tfaw < val) if (Tfaw < val)
Tfaw = val; Tfaw = val;
/* Determine if the DIMMs on this channel support 95°C ETR */
if (pDCTstat->spd_data.spd_bytes[dct + i][SPD_Thermal] & 0x1)
Etr[dct] = 1;
} /* Dimm Present */ } /* Dimm Present */
} }
@ -4248,6 +4255,9 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
dev = pDCTstat->dev_dct; dev = pDCTstat->dev_dct;
dword = Get_NB32_DCT(dev, dct, 0x8c); /* DRAM Timing High */ dword = Get_NB32_DCT(dev, dct, 0x8c); /* DRAM Timing High */
if (Etr[dct])
val = 3; /* Tref = 3.9us */
else
val = 2; /* Tref = 7.8us */ val = 2; /* Tref = 7.8us */
dword &= ~(0x3 << 16); dword &= ~(0x3 << 16);
dword |= (val & 0x3) << 16; dword |= (val & 0x3) << 16;

1
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
View File

@ -232,6 +232,7 @@
#define SPD_tRTPmin 27 #define SPD_tRTPmin 27
#define SPD_Upper_tFAW 28 #define SPD_Upper_tFAW 28
#define SPD_tFAWmin 29 #define SPD_tFAWmin 29
#define SPD_Thermal 31
#define SPD_RefRawCard 62 #define SPD_RefRawCard 62
#define SPD_AddressMirror 63 #define SPD_AddressMirror 63