northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devices
When an Extended Temperature Range DIMM is installed on a channel the refresh rate should be increased per the BKDG recommendations to allow correct operation at higher temperature ranges. Set fast refresh on a channel if an ETR DIMM is installed on that channel. Change-Id: I7a085d34efc78f3f0794a5cb33b88f27a5e6d54e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13144 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -3993,6 +3993,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
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u32 DramTimingLo, DramTimingHi;
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u8 tCK16x;
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u16 Twtr;
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uint8_t Etr[2];
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u8 LDIMM;
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u8 MTB16x;
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u8 byte;
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@ -4011,6 +4012,8 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
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Trc = 0;
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Twr = 0;
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Twtr = 0;
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for (i=0; i < 2; i++)
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Etr[i] = 0;
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for (i=0; i < 4; i++)
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Trfc[i] = 0;
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Tfaw = 0;
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@ -4077,6 +4080,10 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
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val *= MTB16x;
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if (Tfaw < val)
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Tfaw = val;
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/* Determine if the DIMMs on this channel support 95°C ETR */
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if (pDCTstat->spd_data.spd_bytes[dct + i][SPD_Thermal] & 0x1)
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Etr[dct] = 1;
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} /* Dimm Present */
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}
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@ -4248,6 +4255,9 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
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dev = pDCTstat->dev_dct;
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dword = Get_NB32_DCT(dev, dct, 0x8c); /* DRAM Timing High */
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if (Etr[dct])
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val = 3; /* Tref = 3.9us */
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else
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val = 2; /* Tref = 7.8us */
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dword &= ~(0x3 << 16);
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dword |= (val & 0x3) << 16;
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@ -232,6 +232,7 @@
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#define SPD_tRTPmin 27
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#define SPD_Upper_tFAW 28
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#define SPD_tFAWmin 29
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#define SPD_Thermal 31
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#define SPD_RefRawCard 62
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#define SPD_AddressMirror 63
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