mb/google/poppy/variants/nami: Update GPIOs
Updating some GPIOs based on changes in the latest schematics. Also
renaming signals to match that of latest schematics.
BUG=b:73749640
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Make sure different SKUs still boot.
Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shelley Chen
Patrick Georgi
parent
a8a717de30
commit
a2e17586dc
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@ -50,7 +50,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_A16),
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/* A17 : SD_PWR_EN# ==> NC */
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PAD_CFG_NC(GPP_A17),
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/* A18 : ISH_GP0 ==> NC */
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/* A18 : ISH_GP0 ==> EMMC_RST#L_R_SOC (unstuffed) */
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PAD_CFG_NC(GPP_A18),
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/* A19 : ISH_GP1 ==> NC */
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PAD_CFG_NC(GPP_A19),
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@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13 : PLTRST# ==> PLT_RST#_PCH */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14 : SPKR ==> NC */
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/* B14 : SPKR ==> EC_GPP_B14 (rsvd for later) */
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PAD_CFG_NC(GPP_B14),
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/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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@ -109,20 +109,20 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_B21),
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/* B22 : GSPI1_MOSI ==> NC(TP30) */
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PAD_CFG_NC(GPP_B22),
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/* B23 : SM1ALERT# ==> NC */
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/* B23 : SM1ALERT# ==> SOC_SML1ALERT# (unstuffed) */
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PAD_CFG_NC(GPP_B23),
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/* C0 : SMBCLK ==> NC */
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PAD_CFG_NC(GPP_C0),
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/* C1 : SMBDATA ==> NC */
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PAD_CFG_NC(GPP_C1),
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/* C0 : SMBCLK ==> SOC_SMBCLK */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* C1 : SMBDATA ==> SOC_SMBDATA */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* C2 : SMBALERT# ==> NC(TP917) */
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PAD_CFG_NC(GPP_C2),
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/* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */
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PAD_CFG_GPO(GPP_C3, 0, DEEP),
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/* C4 : SML0DATA ==> NC */
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PAD_CFG_NC(GPP_C4),
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/* C5 : SML0ALERT# ==> NC */
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/* C5 : SML0ALERT# ==> SOC_SML0ALERT# (unstuffed) */
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PAD_CFG_NC(GPP_C5),
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/* C6 : SM1CLK ==> EC_IN_RW_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),
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@ -156,12 +156,12 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* C22 : UART2_RTS# ==> NC */
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/* C22 : UART2_RTS# ==> NC(TP926) */
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PAD_CFG_NC(GPP_C22),
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/* C23 : UART2_CTS# ==> PCH_WP */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
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/* D0 : SPI1_CS# ==> NC */
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/* D0 : SPI1_CS# ==> DDR_CHB_EN (for debugging) */
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PAD_CFG_NC(GPP_D0),
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/* D1 : SPI1_CLK ==> PEN_IRQ# */
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PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),
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@ -181,45 +181,45 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_D8),
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/* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
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PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST),
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/* D10 : ISH_SPI_CLK ==> NC(TP29) */
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/* D10 : ISH_SPI_CLK ==> SPKR_RST_L (unstuffed) */
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PAD_CFG_NC(GPP_D10),
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/* D11 : ISH_SPI_MISO ==> NC */
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/* D11 : ISH_SPI_MISO ==> DCI_CLK (debug header) */
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PAD_CFG_NC(GPP_D11),
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/* D12 : ISH_SPI_MOSI ==> NC */
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/* D12 : ISH_SPI_MOSI ==> DCI_DATA (debug header) */
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PAD_CFG_NC(GPP_D12),
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/* D13 : ISH_UART0_RXD ==> NC */
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/* D13 : ISH_UART0_RXD ==> H1_BOOT_UART_RX (unstuffed) */
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PAD_CFG_NC(GPP_D13),
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/* D14 : ISH_UART0_TXD ==> NC */
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/* D14 : ISH_UART0_TXD ==> H1_BOOT_UART_TX (unstuffed) */
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PAD_CFG_NC(GPP_D14),
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/* D15 : ISH_UART0_RTS# ==> NC */
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PAD_CFG_NC(GPP_D15),
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/* D16 : ISH_UART0_CTS# ==> NC */
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PAD_CFG_NC(GPP_D16),
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/* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1 */
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/* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1_R */
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PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
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/* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0 */
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/* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0_R */
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0 */
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/* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0_R */
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PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
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/* D21 : SPI1_IO2 ==> NC */
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/* D21 : SPI1_IO2 ==> DDR_CHA_EN (debugging) */
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PAD_CFG_NC(GPP_D21),
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/* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */
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PAD_CFG_GPO(GPP_D22, 1, DEEP),
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/* D23 : I2S_MCLK ==> NC */
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/* D23 : I2S_MCLK ==> I2S_1_MCLK */
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PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
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/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
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/* E1 : SATAXPCIE1 ==> PEN_EJECT_ODL - for wake event */
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PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, NONE),
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/* E2 : SATAXPCIE2 ==> NC(TP916) */
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PAD_CFG_NC(GPP_E2),
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/* E2 : SATAXPCIE2 ==> WLAN_OFF# */
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PAD_CFG_GPO(GPP_E2, 1, DEEP),
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/* E3 : CPU_GP0 ==> TRACKPAD_INT# */
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PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST),
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/* E4 : SATA_DEVSLP0 ==> NC(TP914) */
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PAD_CFG_NC(GPP_E4),
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/* E5 : SATA_DEVSLP1 ==> DEVSLP1 */
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PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
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/* E5 : SATA_DEVSLP1 ==> NC(TP928) */
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PAD_CFG_NC(GPP_E5),
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/* E6 : SATA_DEVSLP2 ==> NC(TP915) */
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PAD_CFG_NC(GPP_E6),
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/* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */
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@ -238,10 +238,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
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/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
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PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
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/* E15 : DDPD_HPD2 ==> PCH_MEM_CONFIG4 */
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/* E15 : DDPD_HPD2 ==> DDR_SEL */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* E16 : DDPE_HPD3 ==> PCH_GPP_E16 */
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PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT),
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/* E16 : DDPE_HPD3 ==> TRACKPAD_INT# */
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PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT),
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/* E17 : EDP_HPD ==> EDP_HPD */
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* E18 : DDPB_CTRLCLK ==> SOC_DP1_CTRL_CLK */
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@ -254,15 +254,15 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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/* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */
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PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT),
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/* E23 : DDPD_CTRLDATA ==> NC */
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/* E23 : DDPD_CTRLDATA ==> NC(TP17)*/
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PAD_CFG_NC(GPP_E23),
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/* The next 4 pads are for bit banging the amplifiers, default to I2S */
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/* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
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/* F0 : I2S2_SCLK ==> I2S2_2_BCLK_R */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
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/* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
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/* F1 : I2S2_SFRM ==> I2S2_2_FS_LRC */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
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/* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
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/* F2 : I2S2_TXD ==> I2S2_2_TX_DAC */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
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/* F3 : I2S2_RXD ==> NC */
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PAD_CFG_NC(GPP_F3),
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@ -274,35 +274,35 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
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/* F7 : I2C3_SCL ==> I2C_3_SCL */
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PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
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/* F8 : I2C4_SDA ==> NC */
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/* F8 : I2C4_SDA ==> I2C_4_SDA (unstuffed) */
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PAD_CFG_NC(GPP_F8),
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/* F9 : I2C4_SCL ==> NC */
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/* F9 : I2C4_SCL ==> I2C_4_SCL (unstuffed) */
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PAD_CFG_NC(GPP_F9),
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/* F10 : I2C5_SDA ==> NC */
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PAD_CFG_NC(GPP_F10),
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/* F11 : I2C5_SCL ==> NC */
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PAD_CFG_NC(GPP_F11),
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/* F12 : EMMC_CMD ==> EMMC_CMD */
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/* F12 : EMMC_CMD ==> EMMC_1_CMD */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* F13 : EMMC_DATA0 ==> EMMC_DATA0 */
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/* F13 : EMMC_DATA0 ==> EMMC_1_D0 */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* F14 : EMMC_DATA1 ==> EMMC_DATA1 */
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/* F14 : EMMC_DATA1 ==> EMMC_1_D1 */
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PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* F15 : EMMC_DATA2 ==> EMMC_DATA2 */
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/* F15 : EMMC_DATA2 ==> EMMC_1_D2 */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* F16 : EMMC_DATA3 ==> EMMC_DATA3 */
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/* F16 : EMMC_DATA3 ==> EMMC_1_D3 */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* F17 : EMMC_DATA4 ==> EMMC_DATA4 */
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/* F17 : EMMC_DATA4 ==> EMMC_1_D4 */
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PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* F18 : EMMC_DATA5 ==> EMMC_DATA5 */
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/* F18 : EMMC_DATA5 ==> EMMC_1_D5 */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* F19 : EMMC_DATA6 ==> EMMC_DATA6 */
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/* F19 : EMMC_DATA6 ==> EMMC_1_D6 */
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* F20 : EMMC_DATA7 ==> EMMC_DATA7 */
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/* F20 : EMMC_DATA7 ==> EMMC_1_D7 */
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* F21 : EMMC_RCLK ==> EMMC_RCLK */
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/* F21 : EMMC_RCLK ==> EMMC_1_RCLK */
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* F22 : EMMC_CLK ==> EMMC_CLK */
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/* F22 : EMMC_CLK ==> EMMC_1_CLK */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* F23 : RSVD ==> NC */
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PAD_CFG_NC(GPP_F23),
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@ -321,7 +321,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_G5),
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/* G6 : SD_CLK ==> NC */
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PAD_CFG_NC(GPP_G6),
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/* G7 : SD_WP ==> NC */
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/* G7 : SD_WP ==> SD_WP (not needed) */
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PAD_CFG_NC(GPP_G7),
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/* GPD0: BATLOW# ==> PCH_BATLOW# */
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