diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 57c4e65e70..cf64c4bb89 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -196,6 +196,7 @@ chip soc/intel/cannonlake
 
 	# PCIe port 13 for M.2 2280 SSD
 	register "PcieRpEnable[12]" = "1"
+	register "PcieRpLtrEnable[12]" = "1"
 	register "PcieClkSrcUsage[4]" = "12"
 	register "PcieClkSrcClkReq[4]" = "4"
 
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 27c0913c6f..96146baf1e 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -197,6 +197,7 @@ chip soc/intel/cannonlake
 
 	# PCIe port 13 for M.2 2280 SSD
 	register "PcieRpEnable[12]" = "1"
+	register "PcieRpLtrEnable[12]" = "1"
 	register "PcieClkSrcUsage[2]" = "12"
 	register "PcieClkSrcClkReq[2]" = "2"