From a3121b0b2fca0a1f568fe66e5ca3baed1be8acee Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 May 2019 13:46:49 +0200 Subject: [PATCH] sb/intel/lynxpoint: Use common final SPI OPs setup Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33039 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/lpc.c | 6 ++--- src/southbridge/intel/lynxpoint/pch.h | 36 --------------------------- 2 files changed, 2 insertions(+), 40 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b0f57c122b..4efb83e05e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -36,6 +36,7 @@ #include #include #include +#include #define NMI_OFF 0 @@ -960,10 +961,7 @@ static unsigned long southbridge_write_acpi_tables(struct device *device, static void lpc_final(struct device *dev) { - RCBA16(0x3894) = SPI_OPPREFIX; - RCBA16(0x3896) = SPI_OPTYPE; - RCBA32(0x3898) = SPI_OPMENU_LOWER; - RCBA32(0x389c) = SPI_OPMENU_UPPER; + spi_finalize_ops(); if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) outb(APM_CNT_FINALIZE, APM_CNT); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 93c2bc5703..626d22d57f 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -746,42 +746,6 @@ void mainboard_config_superio(void); #define FDOC 0xb0 #define FDOD 0xb4 -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */