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mb/intel/tglrvp: Add pin mux for Camera 

Add additional pin mux for I2C3, I2C5 for Camera.
These pin muxes were done in FSPs, these pin muxes are for bypassing
pin muxes in FSPs.

BUG=none
BRANCH=none
TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera

Simple test method to check camera: capture image by below commands from
OS console
>media-ctl -V "\"Intel IPU6 CSI-2 5\":0 [fmt:SGRBG10/3280x2464]"
>media-ctl -V "\"Intel IPU6 CSI-2 5\":1 [fmt:SGRBG10/3280x2464]"
>media-ctl -l "\"ov8856 18-0010\":0 -> \"Intel IPU6 CSI-2 5\":0[1]"
>media-ctl -V "\"Intel IPU6 CSI2 BE\":0 [fmt:SGRBG10/3280x2464]"
>media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [crop:(0,0)/3280x2464]"
>media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [fmt:SGRBG10/3280x2464]"
>media-ctl -l "\"Intel IPU6 CSI-2 5\":1 -> \"Intel IPU6 CSI2 BE\":0[1]"
>media-ctl -l "\"Intel IPU6 CSI2 BE\":1 -> \"Intel IPU6 CSI2 BE capture\":0[1]"
>yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10
$(media-ctl -e "Intel IPU6 CSI2 BE capture")

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39201
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-02-28 23:31:05 -08:00 committed by Patrick Georgi
parent a3eb3df01c
commit a317353f42
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
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@ -24,6 +24,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
/* Camera */
PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */
PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */
PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */
PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */
PAD_CFG_GPO(GPP_B23, 0, PLTRST),
PAD_CFG_GPO(GPP_C15, 0, PLTRST),
PAD_CFG_GPO(GPP_R6, 0, PLTRST),