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AMD/stoneyridge: Fix SATA reset inconsistency 

At AGESA AmdInitReset, SATA enable and IDE enable (elements of
FCH_RESET_INTERFACE) are programmed twice (before calling AGESA
for AmdInitReset and from said AGESA function call out), using
different functions with different results. The first would result
in TRUE/FALSE, the second set would result in TRUE/TRUE. Use the
functions of the second set within the first set, and remove them
from the second set.

BUG=b:71754828
TEST=Build kahlle without the change, boot and record output. Rebuild
kahlee with the change, boot and record output. Compare both outputs,
the should be no change except in timing.

Change-Id: I326fcc8801542aa7feef286d02abdfe63354cdd0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Richard Spiegel 2018-01-16 13:25:40 -07:00 committed by Martin Roth
parent 2ce90903b0
commit a318d2812d
2 changed files with 2 additions and 4 deletions
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2
src/soc/amd/stoneyridge/BiosCallOuts.c
View File

@ -35,8 +35,6 @@ AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FCH_RESET_DATA_BLOCK *FchParams_reset;
FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams_reset->FchReset.SataEnable = sb_sata_enable();
FchParams_reset->FchReset.IdeEnable = sb_ide_enable();
/* Get platform specific configuration changes */
platform_FchParams_reset(FchParams_reset);

4
src/soc/amd/stoneyridge/southbridge.c
View File

@ -41,8 +41,8 @@ static int is_sata_config(void)
void SetFchResetParams(FCH_RESET_INTERFACE *params)
{
params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE);
params->SataEnable = is_sata_config();
params->IdeEnable = !params->SataEnable;
params->SataEnable = sb_sata_enable();
params->IdeEnable = sb_ide_enable();
}
void SetFchEnvParams(FCH_INTERFACE *params)