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mb/google/brya/var/kano: Update GPIO table for speak and dmic 

Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1)
Set GPIO GPP_S0 ~ GPP_S3 to NF4 and GPP_R6 ~ GPP_R7 to NF3.

BUG=b:204844177 b:202913826
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
David Wu 2021-11-03 12:31:06 +08:00 committed by Patrick Georgi
parent 663a61ed91
commit a3260fde92
2 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/google/brya/variants/kano/fw_config.c
View File

@ -8,8 +8,8 @@
static const struct pad_config dmic_enable_pads[] = { static const struct pad_config dmic_enable_pads[] = {
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* DMIC_CLK1_R */ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* DMIC_DATA1_R */ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */
}; };
static const struct pad_config dmic_disable_pads[] = { static const struct pad_config dmic_disable_pads[] = {
@ -24,10 +24,10 @@ static const struct pad_config i2s_enable_pads[] = {
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), /* I2S_PCH_TX_SPKR_RX_R */ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), /* I2S_PCH_RX_SPKR_TX */ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
}; };
static const struct pad_config i2s_disable_pads[] = { static const struct pad_config i2s_disable_pads[] = {

12
src/mainboard/google/brya/variants/kano/gpio.c
View File

@ -82,18 +82,18 @@ static const struct pad_config override_gpio_table[] = {
/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
/* R6 : I2S2_TXD ==> DMIC_CLK1_R */ /* R6 : I2S2_TXD ==> DMIC_CLK1_R */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
/* R7 : I2S2_RXD ==> DMIC_DATA1_R */ /* R7 : I2S2_RXD ==> DMIC_DATA1_R */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
/* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
/* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
/* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
/* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
/* GPD11: LANPHYC ==> NC */ /* GPD11: LANPHYC ==> NC */
PAD_NC(GPD11, NONE), PAD_NC(GPD11, NONE),