arch/x86: Introduce ARCH_ALL_STAGES_X86_32

Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.

Alder Lake is not yet complete, so it has been skipped for now.

Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-09-25 10:20:11 +02:00 committed by Nico Huber
parent 2db7790795
commit a32df26ec0
33 changed files with 39 additions and 128 deletions

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@ -28,6 +28,13 @@ config ARCH_RAMSTAGE_X86_32
bool bool
select ARCH_X86 select ARCH_X86
config ARCH_ALL_STAGES_X86_32
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
# stage selectors for x64 # stage selectors for x64
config ARCH_BOOTBLOCK_X86_64 config ARCH_BOOTBLOCK_X86_64

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@ -6,10 +6,7 @@ config CPU_AMD_AGESA
default y if CPU_AMD_AGESA_FAMILY15_TN default y if CPU_AMD_AGESA_FAMILY15_TN
default y if CPU_AMD_AGESA_FAMILY16_KB default y if CPU_AMD_AGESA_FAMILY16_KB
default n default n
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select DRIVERS_AMD_PI select DRIVERS_AMD_PI
select TSC_SYNC_LFENCE select TSC_SYNC_LFENCE
select UDELAY_LAPIC select UDELAY_LAPIC

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@ -6,10 +6,7 @@ config CPU_AMD_PI
default y if CPU_AMD_PI_00730F01 default y if CPU_AMD_PI_00730F01
default y if CPU_AMD_PI_00660F01 default y if CPU_AMD_PI_00660F01
default n default n
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select DRIVERS_AMD_PI select DRIVERS_AMD_PI
select TSC_SYNC_LFENCE select TSC_SYNC_LFENCE
select UDELAY_LAPIC select UDELAY_LAPIC

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@ -6,10 +6,7 @@ if CPU_INTEL_HASWELL
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select MMX select MMX
select SSE2 select SSE2
select UDELAY_TSC select UDELAY_TSC

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@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_1067X config CPU_INTEL_MODEL_1067X
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE2 select SSE2
select UDELAY_TSC select UDELAY_TSC
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER

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@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_106CX config CPU_INTEL_MODEL_106CX
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE2 select SSE2
select UDELAY_TSC select UDELAY_TSC
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER

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@ -5,10 +5,7 @@ if CPU_INTEL_MODEL_2065X
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE2 select SSE2
select UDELAY_TSC select UDELAY_TSC
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER

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@ -5,10 +5,7 @@ if CPU_INTEL_MODEL_206AX
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select MMX select MMX
select SSE2 select SSE2
select UDELAY_TSC select UDELAY_TSC

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@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_65X config CPU_INTEL_MODEL_65X
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS

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@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_67X config CPU_INTEL_MODEL_67X
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS

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@ -2,8 +2,5 @@
config CPU_INTEL_MODEL_68X config CPU_INTEL_MODEL_68X
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS

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@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_6BX config CPU_INTEL_MODEL_6BX
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS

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@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_6EX config CPU_INTEL_MODEL_6EX
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE2 select SSE2
select UDELAY_TSC select UDELAY_TSC
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER

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@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_6FX config CPU_INTEL_MODEL_6FX
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE2 select SSE2
select UDELAY_TSC select UDELAY_TSC
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER

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@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_6XX config CPU_INTEL_MODEL_6XX
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS

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@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_F2X config CPU_INTEL_MODEL_F2X
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select SMM_ASEG select SMM_ASEG
select CPU_INTEL_COMMON select CPU_INTEL_COMMON

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@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_F3X config CPU_INTEL_MODEL_F3X
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_HYPERTHREADING select CPU_INTEL_COMMON_HYPERTHREADING

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@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_F4X config CPU_INTEL_MODEL_F4X
bool bool
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS

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@ -19,9 +19,6 @@ config CPU_QEMU_X86_32
bool bool
default n if CPU_QEMU_X86_64 default n if CPU_QEMU_X86_64
default y default y
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_POSTCAR_X86_32 select ARCH_POSTCAR_X86_32
select ARCH_RAMSTAGE_X86_32
endif endif

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@ -9,10 +9,7 @@ if SOC_AMD_STONEYRIDGE
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
select ACPI_AMD_HARDWARE_SLEEP_VALUES select ACPI_AMD_HARDWARE_SLEEP_VALUES
select COLLECT_TIMESTAMPS_NO_TSC select COLLECT_TIMESTAMPS_NO_TSC

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@ -21,10 +21,7 @@ config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_NO_PCAT_8259 select ACPI_NO_PCAT_8259
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
# CPU specific options # CPU specific options

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@ -8,10 +8,7 @@ if SOC_INTEL_BAYTRAIL
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED

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@ -8,10 +8,7 @@ if SOC_INTEL_BRASWELL
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS

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@ -8,10 +8,7 @@ if SOC_INTEL_BROADWELL
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT

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@ -74,10 +74,7 @@ config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_NHLT select ACPI_NHLT
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS

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@ -9,10 +9,7 @@ if SOC_INTEL_DENVERTON_NS
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select DEBUG_GPIO select DEBUG_GPIO

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@ -8,10 +8,7 @@ if SOC_INTEL_ELKHARTLAKE
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS

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@ -8,10 +8,7 @@ if SOC_INTEL_ICELAKE
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS

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@ -8,10 +8,7 @@ if SOC_INTEL_JASPERLAKE
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS

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@ -9,10 +9,7 @@ if SOC_INTEL_QUARK
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select NO_MMCONF_SUPPORT select NO_MMCONF_SUPPORT
select REG_SCRIPT select REG_SCRIPT
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0

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@ -19,10 +19,7 @@ config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_NHLT select ACPI_NHLT
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS

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@ -8,10 +8,7 @@ if SOC_INTEL_TIGERLAKE
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS

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@ -25,10 +25,7 @@ if XEON_SP_COMMON_BASE
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ARCH_BOOTBLOCK_X86_32 select ARCH_ALL_STAGES_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CPU_INTEL_COMMON select CPU_INTEL_COMMON