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intel/smm/gen1: Split alternative SMRR register function 

The non-alternative one will have inlined version available
with the new header.

Change-Id: I208ac84fdf5d8041a1901cc2331769cd3a8d6bea
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-08-12 10:36:47 +03:00
parent 4913d8aed0
commit a347630641
1 changed files with 27 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/cpu/intel/smm/gen1/smmrelocate.c
View File

@ -78,12 +78,8 @@ bool cpu_has_alternative_smrr(void)
} }
} }
static void write_smrr(struct smm_relocation_params *relo_params) static void write_smrr_alt(struct smm_relocation_params *relo_params)
{ {
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
if (cpu_has_alternative_smrr()) {
msr_t msr; msr_t msr;
msr = rdmsr(IA32_FEATURE_CONTROL); msr = rdmsr(IA32_FEATURE_CONTROL);
/* SMRR enabled and feature locked */ /* SMRR enabled and feature locked */
@ -93,13 +89,22 @@ static void write_smrr(struct smm_relocation_params *relo_params)
"SMRR not enabled, skip writing SMRR...\n"); "SMRR not enabled, skip writing SMRR...\n");
return; return;
} }
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base); wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
} else { }
static void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
} }
}
static void fill_in_relocation_params(struct smm_relocation_params *params) static void fill_in_relocation_params(struct smm_relocation_params *params)
{ {
@ -235,7 +240,12 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
/* Write EMRR and SMRR MSRs based on indicated support. */ /* Write EMRR and SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR); mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0) if (!(mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0))
return;
if (cpu_has_alternative_smrr())
write_smrr_alt(relo_params);
else
write_smrr(relo_params); write_smrr(relo_params);
} }