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soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 

Now that the PCIe ports on device 1 are added, rename the aliases for
the PCIe ports on device 2 to have a common naming scheme. For phoenix
the device alias names are based on the device and function number the
bridge is connected to.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-02-03 01:42:52 +01:00
parent bee5c6084c
commit a35b9282cf
3 changed files with 13 additions and 12 deletions
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6
src/mainboard/amd/birman/devicetree_phoenix.cb
View File

@ -158,9 +158,9 @@ chip soc/amd/phoenix
device domain 0 on
device ref iommu on end
device ref gpp_bridge_0 on end # GBE
device ref gpp_bridge_1 on end # WIFI
device ref gpp_bridge_2 on end # NVMe SSD
device ref gpp_bridge_2_1 on end # GBE
device ref gpp_bridge_2_2 on end # WIFI
device ref gpp_bridge_2_3 on end # NVMe SSD
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)

6
src/mainboard/amd/mayan/devicetree_phoenix.cb
View File

@ -158,9 +158,9 @@ chip soc/amd/phoenix
device domain 0 on
device ref iommu on end
device ref gpp_bridge_0 on end # GBE
device ref gpp_bridge_1 on end # WIFI
device ref gpp_bridge_2 on end # NVMe SSD
device ref gpp_bridge_2_1 on end # GBE
device ref gpp_bridge_2_2 on end # WIFI
device ref gpp_bridge_2_3 on end # NVMe SSD
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)

13
src/soc/amd/phoenix/chipset.cb
View File

@ -17,12 +17,13 @@ chip soc/amd/phoenix
device pci 01.4 alias gpp_bridge_1_4 off ops amd_external_pcie_gpp_ops end
device pci 02.0 on end # Dummy Host Bridge, do not disable
device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end
device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end
device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
# The PCIe GPP aliases in this SoC match the device and function numbers
device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end
device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end
device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy Host Bridge, do not disable
device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A