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soc/intel/mtl: Hook up Lp5CccConfig FSP UPD 

Hook up Lp5CccConfig FSP UPD for Intel MeteorLake.

BUG=b:243734885
TEST=Built and booted on Google Rex. Verified the UPD value in MRC log.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Kapil Porwal 2022-08-25 10:25:26 +00:00 committed by Subrata Banik
parent 8680882762
commit a35c0e81b6
1 changed files with 1 additions and 0 deletions
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1
src/soc/intel/meteorlake/meminit.c
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@ -25,6 +25,7 @@ static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg)
static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp5x_config)
{
mem_cfg->DqPinsInterleaved = 0;
mem_cfg->Lp5CccConfig = lp5x_config->ccc_config;
}
static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config)