All the values should stay untouched or be set automatically by the resource

allocator. If that does not work out, they should be set in the code. Setting
them in Kconfig is the worst possible thing to do.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-12-26 16:49:57 +00:00 committed by Stefan Reinauer
parent 2d1d9cebff
commit a35eb2c5e2
2 changed files with 9 additions and 41 deletions

View File

@ -24,42 +24,23 @@
#include <device/pci_ids.h>
#include <console/console.h>
/**
* The following should be set in the mainboard-specific Kconfig file.
*/
#if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \
!defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \
!defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION))
#error "you must supply these values in your mainboard-specific Kconfig file"
#endif
/* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */
/* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */
/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */
/**
* This driver takes the values from Kconfig and loads them in the registers.
*/
static void dec_21143_enable(device_t dev)
{
printk(BIOS_DEBUG, "Initializing DECchip 21143\n");
// The resource allocator should do this. If not, it needs to be fixed
// differently.
#if 0
/* Command and status configuration (offset 0x04) */
pci_write_config32(dev, 0x04,
CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION);
pci_write_config32(dev, 0x04, 0x02800107);
printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n",
pci_read_config32(dev, 0x04));
/* Cache line size (offset 0x0C) */
pci_write_config8(dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE);
printk(BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n",
pci_read_config32(dev, 0x0C));
/* Expansion ROM base address (offset 0x30) */
pci_write_config32(dev, 0x30,
CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS);
printk(BIOS_DEBUG, "0x30 = %08x (0x00000000)\n",
pci_read_config32(dev, 0x30));
pci_write_config8(dev, 0x0C, 0x00);
printk(BIOS_DEBUG, "0x0c = %08x (00)\n",
pci_read_config8(dev, 0x0C));
#endif
}
static struct device_operations dec_21143_ops = {
@ -73,5 +54,5 @@ static struct device_operations dec_21143_ops = {
static const struct pci_driver dec_21143_driver __pci_driver = {
.ops = &dec_21143_ops,
.vendor = PCI_VENDOR_ID_DEC,
.device = PCI_DEVICE_ID_DEC_21142,
.device = PCI_DEVICE_ID_DEC_21142, // FIXME wrong ID?
};

View File

@ -45,19 +45,6 @@ config IRQ_SLOT_COUNT
int
default 22
## Configuration items for the ethernet adaptors
config DEC21143_CACHE_LINE_SIZE
hex
default 0x00000000
config DEC21143_EXPANSION_ROM_BASE_ADDRESS
hex
default 0x00000000
config DEC21143_COMMAND_AND_STATUS_CONFIGURATION
hex
default 0x02800107
## Configuration for the PCMCIA-Cardbus controller.
config TI_PCMCIA_CARDBUS_CMDR
hex