From a36a68b02719cb661d35038fa78600d0b890607c Mon Sep 17 00:00:00 2001 From: "chun-jie.chen" Date: Tue, 18 May 2021 23:06:15 +0800 Subject: [PATCH] soc/mediatek/mt8195: Change fsrc source to ulposc Set fsrc source to ulposc_d10 for 26m off low power scenario. Signed-off-by: chun-jie.chen Change-Id: Ifb02d32820944d7cfbbf23de638e9a0e82b5e84d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54870 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8195/pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 9e9718eb7a..30a8f31beb 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -469,7 +469,7 @@ static const struct mux_sel mux_sels[] = { { .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d6_d8 */ /* CLK_CFG_29 */ { .id = TOP_DVIO_DGI_REF_SEL, .sel = 1 }, /* 1: in_dgi_ck */ - { .id = TOP_SRCK_SEL, .sel = 1 }, /* 1: xtal_26m_ck */ + { .id = TOP_SRCK_SEL, .sel = 0 }, /* 0: ulposc_d10 */ /* CLK_MISC_CFG_3 */ { .id = TOP_MFG_FAST_SEL, .sel = 1 }, /* 1: AD_MFGPLL_OPP_CK */ };