AMD boards: routing.asl: Uniformly start `Package()` with capital letter
In commit Rudolf Marek discovered, that it is not uniformly written. As »ASL names are not case-sensitive and will be converted to upper case.« [2] this change does not have any functional change. The following command was used to create this patch. $ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),' [1] http://review.coreboot.org/#/c/3318/ [2] http://www.acpi.info/spec40a.htm (18.2.1 ASL Names) Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3516 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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@ -116,7 +116,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -116,7 +116,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -83,7 +83,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -122,7 +122,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -89,7 +89,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -120,7 +120,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -110,7 +110,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
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Package(){0x0001FFFF, 0, 0, 17 },
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package(){0x0001FFFF, 1, 0, 18 },
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Package(){0x0001FFFF, 1, 0, 18 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -100,7 +100,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -83,7 +83,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -122,7 +122,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -110,7 +110,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
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Package(){0x0001FFFF, 0, 0, 17 },
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package(){0x0001FFFF, 1, 0, 18 },
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Package(){0x0001FFFF, 1, 0, 18 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -84,7 +84,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -122,7 +122,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -70,7 +70,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -122,7 +122,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -87,7 +87,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
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Package(){0x0001FFFF, 0, 0, 17 },
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package(){0x0001FFFF, 1, 0, 18 },
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Package(){0x0001FFFF, 1, 0, 18 },
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/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -84,7 +84,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -84,7 +84,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -84,7 +84,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -116,7 +116,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -116,7 +116,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -200,7 +200,7 @@ DefinitionBlock (
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#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
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#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
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Name(PRTP, package() {
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Name(PRTP, Package() {
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prt_slot_lnkE(0x0000),
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prt_slot_lnkF(0x0001),
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prt_slot_lnkG(0x0002),
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@ -257,7 +257,7 @@ DefinitionBlock (
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#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
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#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
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Name(PRTA, package() {
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Name(PRTA, Package() {
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prt_slot_gsiE(0x0000),
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prt_slot_gsiF(0x0001),
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prt_slot_gsiG(0x0002),
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@ -84,7 +84,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -84,7 +84,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -89,7 +89,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -120,7 +120,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -89,7 +89,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -122,7 +122,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -122,7 +122,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, 0, 18 },
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package(){0x0001FFFF, 1, 0, 19 },
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Package(){0x0001FFFF, 1, 0, 19 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -83,7 +83,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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@ -83,7 +83,7 @@ Scope(\_SB) {
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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/* Package(){0x0001FFFF, 0, 0, 18 }, */
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/* package(){0x0001FFFF, 1, 0, 19 }, */
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/* Package(){0x0001FFFF, 1, 0, 19 }, */
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, 0, 18 },
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