AMD boards: routing.asl: Uniformly start `Package()` with capital letter

In commit  Rudolf Marek discovered, that it is not uniformly written. As
»ASL names are not case-sensitive and will be converted to upper case.« [2]
this change does not have any functional change.

The following command was used to create this patch.

    $ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),'

[1] http://review.coreboot.org/#/c/3318/
[2] http://www.acpi.info/spec40a.htm
    (18.2.1 ASL Names)

Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3516
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Paul Menzel 2013-06-22 13:47:06 +02:00 committed by Marc Jones
parent eac00d2dbb
commit a390d77966
31 changed files with 32 additions and 32 deletions

View File

@ -116,7 +116,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -116,7 +116,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -83,7 +83,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -122,7 +122,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -89,7 +89,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -120,7 +120,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -110,7 +110,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Package(){0x0001FFFF, 0, 0, 17 },
package(){0x0001FFFF, 1, 0, 18 },
Package(){0x0001FFFF, 1, 0, 18 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -100,7 +100,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -83,7 +83,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -122,7 +122,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -110,7 +110,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Package(){0x0001FFFF, 0, 0, 17 },
package(){0x0001FFFF, 1, 0, 18 },
Package(){0x0001FFFF, 1, 0, 18 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -84,7 +84,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -122,7 +122,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -70,7 +70,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -122,7 +122,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -87,7 +87,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Package(){0x0001FFFF, 0, 0, 17 },
package(){0x0001FFFF, 1, 0, 18 },
Package(){0x0001FFFF, 1, 0, 18 },
/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -84,7 +84,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -84,7 +84,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -84,7 +84,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -116,7 +116,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -116,7 +116,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -200,7 +200,7 @@ DefinitionBlock (
#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
Name(PRTP, package() {
Name(PRTP, Package() {
prt_slot_lnkE(0x0000),
prt_slot_lnkF(0x0001),
prt_slot_lnkG(0x0002),
@ -257,7 +257,7 @@ DefinitionBlock (
#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
Name(PRTA, package() {
Name(PRTA, Package() {
prt_slot_gsiE(0x0000),
prt_slot_gsiF(0x0001),
prt_slot_gsiG(0x0002),

View File

@ -84,7 +84,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -84,7 +84,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -89,7 +89,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -120,7 +120,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -89,7 +89,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -122,7 +122,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -122,7 +122,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
package(){0x0001FFFF, 1, 0, 19 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -83,7 +83,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },

View File

@ -83,7 +83,7 @@ Scope(\_SB) {
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },