From a396c0a7ee5081ca88acf451fd85ef5efb7bf3e7 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 12 Aug 2020 14:54:34 -0700 Subject: [PATCH] mb/google/zork: Update PICASSO_FW_*_POSITION to match new layout CB:44362 ("mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB") updated the flash layout which moved RW_SECTION_A and RW_SECTION_B to different addresses than before. PICASSO_FW_A_POSITION and PICASSO_FW_B_POSITION configs need to be updated accordingly to retain the same behavior as before i.e. amdfw_a/b are placed at the start of FW_MAIN_A/B by placing them right after the CBFS header. This change fixes the value of PICASSO_FW_A_POSITION and PICASSO_FW_B_POSITION to maintain amdfw at the start of RW-A/B CBFS. BUG=b:161949925 Signed-off-by: Furquan Shaikh Change-Id: I177fb38af6380c36397d2a72d5ec00965087d528 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44425 Reviewed-by: Aaron Durbin Reviewed-by: Shelley Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index bf2fe2e36b..1e1b790835 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -129,7 +129,7 @@ config DRIVER_TPM_I2C_ADDR config PICASSO_FW_A_POSITION hex - default 0xFF031040 + default 0xFF012040 depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK help Location of the AMD firmware in the RW_A region. This is the @@ -137,7 +137,7 @@ config PICASSO_FW_A_POSITION config PICASSO_FW_B_POSITION hex - default 0xFF3CF040 + default 0xFF312040 depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK help Location of the AMD firmware in the RW_B region. This is the