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mb/google/skyrim/var/markarth: Update DPTC and STT settings 

According to Thermal table 0518, adjust DPTC and STT settings.

BRANCH=none
BUG=b:273636128
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Id1c1884eabc1ea58148270f39eaca836ccc3fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
This commit is contained in:
John Su 2023-05-19 09:57:48 +08:00 committed by Eric Lai
parent d6b4db159b
commit a398b31108
1 changed files with 15 additions and 2 deletions
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17
src/mainboard/google/skyrim/variants/markarth/overridetree.cb
View File

@ -3,8 +3,21 @@
chip soc/amd/mendocino chip soc/amd/mendocino
# Set Package Power Parameters # Set Package Power Parameters
# Remove the sustained_power_limit_mW when STT is enabled register "thermctl_limit_degreeC" = "92"
register "sustained_power_limit_mW" = "15000"
# STT settings
register "stt_control" = "1"
register "stt_pcb_sensor_count" = "2"
register "stt_error_coeff" = "0x0038"
register "stt_error_rate_coefficient" = "0x0ed9"
register "stt_min_limit" = "15000"
register "stt_skin_temp_apu" = "0x2700"
# STT default mode
register "stt_m1" = "0x036b"
register "stt_m2" = "0x0022"
register "stt_c_apu" = "0xffc1"
register "stt_alpha_apu" = "0x199a"
# set usb3 port force to gen1 # set usb3 port force to gen1
register "usb3_port_force_gen1" = "{ register "usb3_port_force_gen1" = "{