soc/mediatek/mt8192: add apusys init flow

Setup APU mbox's functional configuration registers.

BUG=b:186369803
BRANCH=asurada
TEST=boot asurada correctly

Signed-off-by: Chien-Chih Tseng <chien-chih.tseng@mediatek.com>
Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48622
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/mt8192/Makefile.inc

@@ -42,6 +42,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
 
+ramstage-y += apusys.c
 ramstage-y += ../common/auxadc.c
 ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += devapc.c

src/soc/mediatek/mt8192/apusys.c

@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/apusys.h>
+#include <soc/infracfg.h>
+
+/* INFRA2APU_SRAM_PROT_EN */
+DEFINE_BITFIELD(PROT_EN, 31, 30)
+
+/* MBOX Functional Configuration */
+DEFINE_BITFIELD(LOCK, 0, 0)
+DEFINE_BITFIELD(NO_MPU, 16, 16)
+
+static void dump_apusys_reg(void)
+{
+	int i;
+
+	printk(BIOS_INFO, "INFRA2APU_SRAM_PROT_EN %p = %#x\n",
+	       (void *)&mt8192_infracfg->infra_ao_mm_hang_free,
+	       read32(&mt8192_infracfg->infra_ao_mm_hang_free));
+
+	for (i = 0; i < ARRAY_SIZE(mt8192_apu_mbox); i++) {
+		printk(BIOS_INFO, "APU_MBOX %p = %#x\n",
+		       (void *)&mt8192_apu_mbox[i]->mbox_func_cfg,
+		       read32(&mt8192_apu_mbox[i]->mbox_func_cfg));
+	}
+}
+
+void apusys_init(void)
+{
+	int i;
+
+	SET32_BITFIELDS(&mt8192_infracfg->infra_ao_mm_hang_free, PROT_EN, 0);
+
+	/* Setup MBOX MPU for non secure access */
+	for (i = 0; i < ARRAY_SIZE(mt8192_apu_mbox); i++)
+		SET32_BITFIELDS(&mt8192_apu_mbox[i]->mbox_func_cfg, NO_MPU, 1, LOCK, 1);
+
+	dump_apusys_reg();
+}

src/soc/mediatek/mt8192/include/soc/addressmap.h

@@ -87,6 +87,7 @@ enum {
 	DISP_POSTMASK0_BASE	= IO_PHYS + 0x0400D000,
 	DISP_DITHER0_BASE	= IO_PHYS + 0x0400E000,
 	DSI0_BASE		= IO_PHYS + 0x04010000,
+	APU_MBOX_BASE		= IO_PHYS + 0x09000000,
 };
 
 #endif

src/soc/mediatek/mt8192/include/soc/apusys.h

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_APUSYS_H
+#define SOC_MEDIATEK_MT8192_APUSYS_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8192_apu_mbox_regs {
+	u32 mbox_in[8];
+	u32 mbox_out[8];
+	u32 mbox_reserved1[28];
+	u32 mbox_func_cfg;
+	u32 mbox0_reserved2[19];
+};
+
+check_member(mt8192_apu_mbox_regs, mbox_func_cfg, 0x0b0);
+
+static struct mt8192_apu_mbox_regs * const mt8192_apu_mbox[] = {
+	(void *)APU_MBOX_BASE,
+	(void *)(APU_MBOX_BASE + 0x100),
+	(void *)(APU_MBOX_BASE + 0x500),
+	(void *)(APU_MBOX_BASE + 0x600),
+};
+
+void apusys_init(void);
+#endif  /* SOC_MEDIATEK_MT8192_APUSYS_H */

src/soc/mediatek/mt8192/soc.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <soc/apusys.h>
 #include <soc/devapc.h>
 #include <soc/emi.h>
 #include <soc/mcupm.h>
@@ -17,6 +18,7 @@ static void soc_read_resources(struct device *dev)
 static void soc_init(struct device *dev)
 {
 	mtk_mmu_disable_l2c_sram();
+	apusys_init();
 	dapc_init();
 	mcupm_init();
 	sspm_init();