intel/common/p2sb: Add common p2sb driver
Add common p2sb device driver that will use fixed resource instead dynamic assigned by PCI enumeration. TEST=None Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H
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#define SOC_INTEL_COMMON_BLOCK_P2SB_H
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void p2sb_unhide(void);
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void p2sb_hide(void);
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#endif /* SOC_INTEL_COMMON_BLOCK_P2SB_H */
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config SOC_INTEL_COMMON_BLOCK_P2SB
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bool
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depends on SOC_INTEL_COMMON_BLOCK_PCR
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help
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Intel Processor common P2SB driver
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <rules.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <intelblocks/p2sb.h>
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#define P2SB_E0 0xe0
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#define HIDE_BIT (1 << 0)
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static void p2sb_set_hide_bit(int hide)
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{
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struct device *dev;
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const uint16_t reg = P2SB_E0 + 1;
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const uint8_t mask = HIDE_BIT;
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uint8_t val;
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dev = PCH_DEV_P2SB;
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val = pci_read_config8(dev, reg);
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val &= ~mask;
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if (hide)
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val |= mask;
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pci_write_config8(dev, reg, val);
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}
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void p2sb_unhide(void)
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{
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p2sb_set_hide_bit(0);
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}
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void p2sb_hide(void)
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{
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p2sb_set_hide_bit(1);
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}
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static void read_resources(struct device *dev)
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{
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/*
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* There's only one resource on the P2SB device. It's also already
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* manually set to a fixed address in earlier boot stages.
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*/
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mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB);
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}
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static const struct device_operations device_ops = {
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.read_resources = read_resources,
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.set_resources = DEVICE_NOOP,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_APL_P2SB,
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PCI_DEVICE_ID_INTEL_GLK_P2SB,
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PCI_DEVICE_ID_INTEL_CNL_P2SB,
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0,
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};
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static const struct pci_driver pmc __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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