skylake: read out and report full width of gen_pmcon registers
GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and save the full 32 bits for completeness. BUG=chrome-os-partner:42847 BRANCH=None TEST=Built and booted. Noted output on terminal. Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0 Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286270 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11006 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -124,8 +124,8 @@ struct chipset_power_state {
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uint16_t tco2_sts;
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uint32_t gpe0_sts[4];
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uint32_t gpe0_en[4];
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uint16_t gen_pmcon_a;
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uint16_t gen_pmcon_b;
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uint32_t gen_pmcon_a;
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uint32_t gen_pmcon_b;
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int prev_sleep_state;
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uint16_t hsio_version;
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uint16_t hsio_checksum;
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@ -95,7 +95,7 @@ static void dump_power_state(struct chipset_power_state *ps)
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ps->gpe0_en[0], ps->gpe0_en[1],
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ps->gpe0_en[2], ps->gpe0_en[3]);
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printk(BIOS_DEBUG, "GEN_PMCON: %04x %04x\n",
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printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
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ps->gen_pmcon_a, ps->gen_pmcon_b);
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printk(BIOS_DEBUG, "Previous Sleep State: S%d\n",
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@ -124,8 +124,8 @@ struct chipset_power_state *fill_power_state(void)
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ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
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ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
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ps->gen_pmcon_a = pci_read_config16(PCH_DEV_PMC, GEN_PMCON_A);
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ps->gen_pmcon_b = pci_read_config16(PCH_DEV_PMC, GEN_PMCON_B);
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ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
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ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
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ps->prev_sleep_state = prev_sleep_state(ps);
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