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soc/intel/tigerlake/acpi: Update gpio_op.asl to ASL2.0 syntax 

This change updates gpio_op.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

BUG=none
BRANCH=none
TEST="BUILD for Volteer"

Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib54b3f7da828ce8d232fcea0639077970638f610
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Venkata Krishna Nimmagadda 2020-05-27 14:26:29 -07:00 committed by Patrick Georgi
parent 7051a40b0b
commit a3e228ce15
1 changed files with 15 additions and 16 deletions
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31
src/soc/intel/tigerlake/acpi/gpio_op.asl
View File

@ -11,7 +11,7 @@ Method (GRXS, 1, Serialized)
{
VAL0, 32
}
And (PAD_CFG0_RX_STATE, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0)
Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
Return (Local0)
}
@ -27,7 +27,7 @@ Method (GTXS, 1, Serialized)
{
VAL0, 32
}
And (PAD_CFG0_TX_STATE, VAL0, Local0)
Local0 = PAD_CFG0_TX_STATE & VAL0
Return (Local0)
}
@ -43,7 +43,7 @@ Method (STXS, 1, Serialized)
{
VAL0, 32
}
Or (PAD_CFG0_TX_STATE, VAL0, VAL0)
VAL0 = PAD_CFG0_TX_STATE | VAL0
}
/*
@ -57,7 +57,7 @@ Method (CTXS, 1, Serialized)
{
VAL0, 32
}
And (Not (PAD_CFG0_TX_STATE), VAL0, VAL0)
VAL0 = ~PAD_CFG0_TX_STATE & VAL0
}
/*
@ -76,10 +76,9 @@ Method (GPMO, 2, Serialized)
{
VAL0, 32
}
Store (VAL0, Local0)
And (Not (PAD_CFG0_MODE_MASK), Local0, Local0)
And (ShiftLeft (Arg1, PAD_CFG0_MODE_SHIFT, Arg1), PAD_CFG0_MODE_MASK, Arg1)
Or (Local0, Arg1, VAL0)
Local0 = ~PAD_CFG0_MODE_MASK & VAL0
Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK
VAL0 = Local0 | Arg1
}
/*
@ -97,10 +96,10 @@ Method (GTXE, 2, Serialized)
VAL0, 32
}
If (LEqual (Arg1, 1)) {
And (Not (PAD_CFG0_TX_DISABLE), VAL0, VAL0)
} ElseIf (LEqual (Arg1, 0)){
Or (PAD_CFG0_TX_DISABLE, VAL0, VAL0)
If (Arg1 == 1) {
VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0
} ElseIf (Arg1 == 0){
VAL0 = PAD_CFG0_TX_DISABLE | VAL0
}
}
@ -119,9 +118,9 @@ Method (GRXE, 2, Serialized)
VAL0, 32
}
If (LEqual (Arg1, 1)) {
And (Not (PAD_CFG0_RX_DISABLE), VAL0, VAL0)
} ElseIf (LEqual (Arg1, 0)){
Or (PAD_CFG0_RX_DISABLE, VAL0, VAL0)
If (Arg1 == 1) {
VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0
} ElseIf (Arg1 == 0){
VAL0 = PAD_CFG0_RX_DISABLE | VAL0
}
}