Migrate 206ax to SMM_MODULES
This gets rid of ugly tseg_relocate for bd82x6x.
This is backport of 29ffa54969 to bd82x6x.
Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Vladimir Serbinenko
parent
3c6d36d26f
commit
a3e41c0896
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@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
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select SSE2
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select UDELAY_LAPIC
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select SMM_TSEG
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select SMM_MODULES
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select SUPPORT_CPU_UCODE_IN_CBFS
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select PARALLEL_CPU_INIT
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#select AP_IN_SIPI_WAIT
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@ -8,3 +8,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
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@ -103,6 +103,7 @@ void intel_model_206ax_finalize_smm(void);
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/* Configure power limits for turbo mode */
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void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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void smm_relocate(void);
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#endif
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#endif
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@ -0,0 +1,333 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 ChromeOS Authors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <string.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include "model_206ax.h"
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#define EMRRphysBase_MSR 0x1f4
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#define EMRRphysMask_MSR 0x1f5
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#define UNCORE_EMRRphysBase_MSR 0x2f4
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#define UNCORE_EMRRphysMask_MSR 0x2f5
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#define CORE_THREAD_COUNT_MSR 0x35
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#define SMRR_SUPPORTED (1<<11)
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#define EMRR_SUPPORTED (1<<12)
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struct smm_relocation_params {
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u32 smram_base;
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u32 smram_size;
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u32 ied_base;
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u32 ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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msr_t emrr_base;
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msr_t emrr_mask;
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msr_t uncore_emrr_base;
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msr_t uncore_emrr_mask;
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};
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/* This gets filled in and used during relocation. */
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static struct smm_relocation_params smm_reloc_params;
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static inline void write_smrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
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wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
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}
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static inline void write_emrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->emrr_base.lo, relo_params->emrr_mask.lo);
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wrmsr(EMRRphysBase_MSR, relo_params->emrr_base);
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wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask);
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}
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static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG,
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"Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->uncore_emrr_base.lo,
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relo_params->uncore_emrr_mask.lo);
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wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base);
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wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask);
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}
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/* The relocation work is actually performed in SMM context, but the code
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* resides in the ramstage module. This occurs by trampolining from the default
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* SMRAM entry point to here. */
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static void asmlinkage cpu_smm_do_relocation(void *arg)
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{
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em64t101_smm_state_save_area_t *save_state;
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msr_t mtrr_cap;
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struct smm_relocation_params *relo_params;
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const struct smm_module_params *p;
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const struct smm_runtime *runtime;
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int cpu;
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p = arg;
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runtime = p->runtime;
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relo_params = p->arg;
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cpu = p->cpu;
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if (cpu >= CONFIG_MAX_CPUS) {
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printk(BIOS_CRIT,
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"Invalid CPU number assigned in SMM stub: %d\n", cpu);
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return;
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}
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printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
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/* All threads need to set IEDBASE and SMBASE in the save state area.
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* Since one thread runs at a time during the relocation the save state
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* is the same for all cpus. */
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save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE -
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runtime->save_state_size);
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/* The relocated handler runs with all CPUs concurrently. Therefore
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* stagger the entry points adjusting SMBASE downwards by save state
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* size * CPU num. */
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save_state->smbase = relo_params->smram_base -
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cpu * runtime->save_state_size;
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save_state->iedbase = relo_params->ied_base;
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printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
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save_state->smbase, save_state->iedbase, save_state);
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/* Write EMRR and SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRRcap_MSR);
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if (mtrr_cap.lo & SMRR_SUPPORTED)
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write_smrr(relo_params);
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if (mtrr_cap.lo & EMRR_SUPPORTED) {
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write_emrr(relo_params);
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/* UNCORE_EMRR msrs are package level. Therefore, only
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* configure these MSRs on the BSP. */
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if (cpu == 0)
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write_uncore_emrr(relo_params);
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}
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southbridge_clear_smi_status();
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}
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static u32 northbridge_get_base_reg(device_t dev, int reg)
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{
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u32 value;
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value = pci_read_config32(dev, reg);
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/* Base registers are at 1MiB granularity. */
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value &= ~((1 << 20) - 1);
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return value;
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}
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static void fill_in_relocation_params(device_t dev,
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struct smm_relocation_params *params)
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{
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u32 tseg_size;
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u32 tsegmb;
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u32 bgsm;
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u32 emrr_base;
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u32 emrr_size;
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int phys_bits;
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/* All range registers are aligned to 4KiB */
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const u32 rmask = ~((1 << 12) - 1);
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/* Some of the range registers are dependent on the number of physical
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* address bits supported. */
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phys_bits = cpuid_eax(0x80000008) & 0xff;
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/* The range bounded by the TSEGMB and BGSM registers encompasses the
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* SMRAM range as well as the IED range. However, the SMRAM available
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* to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
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*/
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tsegmb = northbridge_get_base_reg(dev, TSEG);
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bgsm = northbridge_get_base_reg(dev, BGSM);
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tseg_size = bgsm - tsegmb;
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params->smram_base = tsegmb;
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params->smram_size = 4 << 20;
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params->ied_base = tsegmb + params->smram_size;
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params->ied_size = tseg_size - params->smram_size;
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
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params->smrr_mask.hi = 0;
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/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
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emrr_base = (params->ied_base + (2 << 20)) & rmask;
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emrr_size = params->ied_size - (2 << 20);
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/* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
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* on the number of physical address bits supported. */
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params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
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params->emrr_base.hi = 0;
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params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid;
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params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
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/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
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params->uncore_emrr_base.lo = emrr_base;
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params->uncore_emrr_base.hi = 0;
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params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
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MTRRphysMaskValid;
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params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
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}
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static int install_relocation_handler(int num_cpus,
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struct smm_relocation_params *relo_params)
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{
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/* The default SMM entry happens serially at the default location.
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* Therefore, there is only 1 concurrent save state area. Set the
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* stack size to the save state size, and call into the
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* do_relocation handler. */
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int save_state_size = sizeof(em64t101_smm_state_save_area_t);
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = num_cpus,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = 1,
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.handler = &cpu_smm_do_relocation,
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.handler_arg = (void *)relo_params,
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};
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return smm_setup_relocation_handler(&smm_params);
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}
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static void setup_ied_area(struct smm_relocation_params *params)
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{
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char *ied_base;
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struct ied_header ied = {
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.signature = "INTEL RSVD",
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.size = params->ied_size,
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.reserved = {0},
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};
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ied_base = (void *)params->ied_base;
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/* Place IED header at IEDBASE. */
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memcpy(ied_base, &ied, sizeof(ied));
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/* Zero out 32KiB at IEDBASE + 1MiB */
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memset(ied_base + (1 << 20), 0, (32 << 10));
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}
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static int install_permanent_handler(int num_cpus,
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struct smm_relocation_params *relo_params)
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{
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/* There are num_cpus concurrent stacks and num_cpus concurrent save
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* state areas. Lastly, set the stack size to the save state size. */
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int save_state_size = sizeof(em64t101_smm_state_save_area_t);
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = num_cpus,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = num_cpus,
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};
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printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
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relo_params->smram_base);
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return smm_load_module((void *)relo_params->smram_base,
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relo_params->smram_size, &smm_params);
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}
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static int cpu_smm_setup(void)
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{
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device_t dev;
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int num_cpus;
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msr_t msr;
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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fill_in_relocation_params(dev, &smm_reloc_params);
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setup_ied_area(&smm_reloc_params);
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msr = rdmsr(CORE_THREAD_COUNT_MSR);
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num_cpus = msr.lo & 0xffff;
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if (num_cpus > CONFIG_MAX_CPUS) {
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printk(BIOS_CRIT,
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"Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n",
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num_cpus, CONFIG_MAX_CPUS);
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}
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if (install_relocation_handler(num_cpus, &smm_reloc_params)) {
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printk(BIOS_CRIT, "SMM Relocation handler install failed.\n");
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return -1;
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}
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if (install_permanent_handler(num_cpus, &smm_reloc_params)) {
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printk(BIOS_CRIT, "SMM Permanent handler install failed.\n");
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return -1;
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}
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/* Ensure the SMM handlers hit DRAM before performing first SMI. */
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/* TODO(adurbin): Is this really needed? */
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wbinvd();
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return 0;
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}
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void smm_init(void)
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{
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/* Return early if CPU SMM setup failed. */
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if (cpu_smm_setup())
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return;
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southbridge_smm_init();
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/* Initiate first SMI to kick off SMM-context relocation. Note: this
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* SMI being triggered here queues up an SMI in the APs which are in
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* wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI
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* at the SMM_DEFAULT_BASE before jumping to startup vector. */
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southbridge_trigger_smi();
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printk(BIOS_DEBUG, "Relocation complete.\n");
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/* Lock down the SMRAM space. */
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smm_lock();
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}
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void smm_lock(void)
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{
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/* LOCK the SMM memory window and enable normal SMM.
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* After running this function, only a full reset can
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* make the SMM registers writable again.
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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D_LCK | G_SMRAME | C_BASE_SEG);
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}
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@ -36,7 +36,7 @@
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#include "../../../southbridge/intel/i82801dx/i82801dx.h"
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#elif CONFIG_SOUTHBRIDGE_INTEL_SCH
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#include "../../../southbridge/intel/sch/sch.h"
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#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 || CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
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#elif CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
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#include "../../../southbridge/intel/bd82x6x/pch.h"
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#elif CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X
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#include "../../../southbridge/intel/fsp_bd82x6x/pch.h"
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@ -48,10 +48,7 @@
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#if CONFIG_SMM_TSEG
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#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
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#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
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#if CONFIG_NORTHBRIDGE_INTEL_NEHALEM
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#include <northbridge/intel/nehalem/nehalem.h>
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#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
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#else
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@ -99,6 +99,7 @@
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#define TOM 0xa0
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#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
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#define BGSM 0xb4 /* Base GTT Stolen Memory */
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#define TSEG 0xb8 /* TSEG base */
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#define TOLUD 0xbc /* Top of Low Used Memory */
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@ -43,7 +43,6 @@
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#define NMI_OFF 0
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#define ENABLE_ACPI_MODE_IN_COREBOOT 0
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#define TEST_SMM_FLASH_LOCKDOWN 0
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typedef struct southbridge_intel_bd82x6x_config config_t;
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@ -427,58 +426,20 @@ static void enable_clock_gating(device_t dev)
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RCBA32_OR(0x3564, 0x3);
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}
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#if CONFIG_HAVE_SMI_HANDLER
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static void pch_lock_smm(struct device *dev)
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static void pch_set_acpi_mode(void)
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{
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#if TEST_SMM_FLASH_LOCKDOWN
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u8 reg8;
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#endif
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if (!acpi_is_wakeup_s3()) {
|
||||
if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
|
||||
#if ENABLE_ACPI_MODE_IN_COREBOOT
|
||||
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
|
||||
outb(0xe1, 0xb2); // Enable ACPI mode
|
||||
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
#else
|
||||
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
|
||||
outb(0x1e, 0xb2); // Disable ACPI mode
|
||||
outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Don't allow evil boot loaders, kernels, or
|
||||
* userspace applications to deceive us:
|
||||
*/
|
||||
smm_lock();
|
||||
|
||||
#if TEST_SMM_FLASH_LOCKDOWN
|
||||
/* Now try this: */
|
||||
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
|
||||
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
||||
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
|
||||
(reg8&1)?"rw":"ro");
|
||||
reg8 &= ~(1 << 0); /* clear BIOSWE */
|
||||
pci_write_config8(dev, 0xdc, reg8);
|
||||
reg8 |= (1 << 1); /* set BLE */
|
||||
pci_write_config8(dev, 0xdc, reg8);
|
||||
printk(BIOS_DEBUG, "ok.\n");
|
||||
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
||||
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
|
||||
(reg8&1)?"rw":"ro");
|
||||
|
||||
printk(BIOS_DEBUG, "Writing:\n");
|
||||
*(volatile u8 *)0xfff00000 = 0x00;
|
||||
printk(BIOS_DEBUG, "Testing:\n");
|
||||
reg8 |= (1 << 0); /* set BIOSWE */
|
||||
pci_write_config8(dev, 0xdc, reg8);
|
||||
|
||||
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
||||
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
|
||||
(reg8&1)?"rw":"ro");
|
||||
printk(BIOS_DEBUG, "Done.\n");
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
static void pch_disable_smm_only_flashing(struct device *dev)
|
||||
{
|
||||
|
|
@ -572,9 +533,7 @@ static void lpc_init(struct device *dev)
|
|||
|
||||
pch_disable_smm_only_flashing(dev);
|
||||
|
||||
#if CONFIG_HAVE_SMI_HANDLER
|
||||
pch_lock_smm(dev);
|
||||
#endif
|
||||
pch_set_acpi_mode();
|
||||
|
||||
pch_fixups(dev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -66,6 +66,11 @@ void intel_pch_finalize_smm(void);
|
|||
#include "chip.h"
|
||||
void pch_enable(device_t dev);
|
||||
#endif
|
||||
/* These helpers are for performing SMM relocation. */
|
||||
void southbridge_smm_init(void);
|
||||
void southbridge_trigger_smi(void);
|
||||
void southbridge_clear_smi_status(void);
|
||||
|
||||
int pch_silicon_revision(void);
|
||||
int pch_silicon_type(void);
|
||||
int pch_silicon_supported(int type, int rev);
|
||||
|
|
|
|||
|
|
@ -28,10 +28,6 @@
|
|||
#include <cpu/x86/smm.h>
|
||||
#include <string.h>
|
||||
#include "pch.h"
|
||||
#include "northbridge/intel/sandybridge/sandybridge.h"
|
||||
|
||||
extern unsigned char _binary_smm_start;
|
||||
extern unsigned char _binary_smm_end;
|
||||
|
||||
/* While we read PMBASE dynamically in case it changed, let's
|
||||
* initialize it with a sane value
|
||||
|
|
@ -228,15 +224,18 @@ static void smi_set_eos(void)
|
|||
outb(reg8, pmbase + SMI_EN);
|
||||
}
|
||||
|
||||
extern uint8_t smm_relocation_start, smm_relocation_end;
|
||||
|
||||
static void smm_relocate(void)
|
||||
void southbridge_smm_init(void)
|
||||
{
|
||||
u32 smi_en;
|
||||
u16 pm1_en;
|
||||
u32 gpe0_en;
|
||||
|
||||
printk(BIOS_DEBUG, "Initializing SMM handler...");
|
||||
#if CONFIG_ELOG
|
||||
/* Log events from chipset before clearing */
|
||||
pch_log_state();
|
||||
#endif
|
||||
|
||||
printk(BIOS_DEBUG, "Initializing southbridge SMI...");
|
||||
|
||||
pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
|
||||
PMBASE) & 0xff80;
|
||||
|
|
@ -249,10 +248,6 @@ static void smm_relocate(void)
|
|||
return;
|
||||
}
|
||||
|
||||
/* copy the SMM relocation code */
|
||||
memcpy((void *)0x38000, &smm_relocation_start,
|
||||
&smm_relocation_end - &smm_relocation_start);
|
||||
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
dump_smi_status(reset_smi_status());
|
||||
dump_pm1_status(reset_pm1_status());
|
||||
|
|
@ -301,7 +296,10 @@ static void smm_relocate(void)
|
|||
smi_en |= EOS | GBL_SMI_EN;
|
||||
|
||||
outl(smi_en, pmbase + SMI_EN);
|
||||
}
|
||||
|
||||
void southbridge_trigger_smi(void)
|
||||
{
|
||||
/**
|
||||
* There are several methods of raising a controlled SMI# via
|
||||
* software, among them:
|
||||
|
|
@ -320,79 +318,18 @@ static void smm_relocate(void)
|
|||
outb(0x00, 0xb2);
|
||||
}
|
||||
|
||||
static int smm_handler_copied = 0;
|
||||
|
||||
static void smm_install(void)
|
||||
void southbridge_clear_smi_status(void)
|
||||
{
|
||||
device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
|
||||
u32 smm_base = 0xa0000;
|
||||
struct ied_header ied = {
|
||||
.signature = "INTEL RSVD",
|
||||
.size = IED_SIZE,
|
||||
.reserved = {0},
|
||||
};
|
||||
/* Clear SMI status */
|
||||
reset_smi_status();
|
||||
|
||||
/* The first CPU running this gets to copy the SMM handler. But not all
|
||||
* of them.
|
||||
*/
|
||||
if (smm_handler_copied)
|
||||
return;
|
||||
smm_handler_copied = 1;
|
||||
/* Clear PM1 status */
|
||||
reset_pm1_status();
|
||||
|
||||
/* enable the SMM memory window */
|
||||
pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
|
||||
|
||||
#if CONFIG_SMM_TSEG
|
||||
smm_base = pci_read_config32(dev, TSEG) & ~1;
|
||||
#endif
|
||||
|
||||
/* copy the real SMM handler */
|
||||
printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base);
|
||||
memcpy((void *)smm_base, &_binary_smm_start,
|
||||
(size_t)(&_binary_smm_end - &_binary_smm_start));
|
||||
|
||||
/* copy the IED header into place */
|
||||
if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) {
|
||||
/* Top of TSEG region */
|
||||
smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE;
|
||||
printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n",
|
||||
smm_base);
|
||||
memcpy((void *)smm_base, &ied, sizeof(ied));
|
||||
}
|
||||
wbinvd();
|
||||
|
||||
/* close the SMM memory window and enable normal SMM */
|
||||
pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
|
||||
}
|
||||
|
||||
void smm_init(void)
|
||||
{
|
||||
#if CONFIG_ELOG
|
||||
/* Log events from chipset before clearing */
|
||||
pch_log_state();
|
||||
#endif
|
||||
|
||||
/* Put SMM code to 0xa0000 */
|
||||
smm_install();
|
||||
|
||||
/* Put relocation code to 0x38000 and relocate SMBASE */
|
||||
smm_relocate();
|
||||
|
||||
/* We're done. Make sure SMIs can happen! */
|
||||
/* Set EOS bit so other SMIs can occur. */
|
||||
smi_set_eos();
|
||||
}
|
||||
|
||||
void smm_lock(void)
|
||||
{
|
||||
/* LOCK the SMM memory window and enable normal SMM.
|
||||
* After running this function, only a full reset can
|
||||
* make the SMM registers writable again.
|
||||
*/
|
||||
printk(BIOS_DEBUG, "Locking SMM.\n");
|
||||
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
|
||||
D_LCK | G_SMRAME | C_BASE_SEG);
|
||||
}
|
||||
|
||||
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
|
||||
{
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -31,10 +31,6 @@
|
|||
|
||||
#include "nvs.h"
|
||||
|
||||
/* We are using PCIe accesses for now
|
||||
* 1. the chipset can do it
|
||||
* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
|
||||
*/
|
||||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <arch/pci_mmio_cfg.h>
|
||||
#include <southbridge/intel/bd82x6x/me.h>
|
||||
|
|
@ -54,28 +50,12 @@ static u8 smm_initialized = 0;
|
|||
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
|
||||
* by coreboot.
|
||||
*/
|
||||
static global_nvs_t *gnvs = (global_nvs_t *)0x0;
|
||||
static global_nvs_t *gnvs;
|
||||
global_nvs_t *smm_get_gnvs(void)
|
||||
{
|
||||
return gnvs;
|
||||
}
|
||||
|
||||
#if CONFIG_SMM_TSEG
|
||||
static u32 tseg_base = 0;
|
||||
u32 smi_get_tseg_base(void)
|
||||
{
|
||||
if (!tseg_base)
|
||||
tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
|
||||
return tseg_base;
|
||||
}
|
||||
void tseg_relocate(void **ptr)
|
||||
{
|
||||
/* Adjust pointer with TSEG base */
|
||||
if (*ptr && *ptr < (void*)smi_get_tseg_base())
|
||||
*ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base());
|
||||
}
|
||||
#endif
|
||||
|
||||
static void alt_gpi_mask(u16 clr, u16 set)
|
||||
{
|
||||
u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
|
||||
|
|
@ -424,7 +404,7 @@ static void xhci_sleep(u8 slp_typ)
|
|||
}
|
||||
|
||||
|
||||
static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
|
||||
static void southbridge_smi_sleep(void)
|
||||
{
|
||||
u8 reg8;
|
||||
u32 reg32;
|
||||
|
|
@ -439,8 +419,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
|
|||
outb(tmp70, 0x70);
|
||||
outb(tmp72, 0x72);
|
||||
|
||||
void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
|
||||
|
||||
/* First, disable further SMIs */
|
||||
reg8 = inb(pmbase + SMI_EN);
|
||||
reg8 &= ~SLP_SMI_EN;
|
||||
|
|
@ -455,8 +433,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
|
|||
xhci_sleep(slp_typ);
|
||||
|
||||
/* Do any mainboard sleep handling */
|
||||
tseg_relocate((void **)&mainboard_sleep);
|
||||
mainboard_sleep(slp_typ-2);
|
||||
mainboard_smi_sleep(slp_typ-2);
|
||||
|
||||
#if CONFIG_ELOG_GSMI
|
||||
/* Log S3, S4, and S5 entry */
|
||||
|
|
@ -532,13 +509,11 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
|
|||
static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
|
||||
{
|
||||
em64t101_smm_state_save_area_t *state;
|
||||
u32 base = smi_get_tseg_base() + SMM_EM64T101_SAVE_STATE_OFFSET;
|
||||
int node;
|
||||
|
||||
/* Check all nodes looking for the one that issued the IO */
|
||||
for (node = 0; node < CONFIG_MAX_CPUS; node++) {
|
||||
state = (em64t101_smm_state_save_area_t *)
|
||||
(base - (node * 0x400));
|
||||
state = smm_get_save_state(node);
|
||||
|
||||
/* Check for Synchronous IO (bit0==1) */
|
||||
if (!(state->io_misc_info & (1 << 0)))
|
||||
|
|
@ -587,11 +562,10 @@ static void southbridge_smi_gsmi(void)
|
|||
|
||||
static int mainboard_finalized = 0;
|
||||
|
||||
static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
|
||||
static void southbridge_smi_apmc(void)
|
||||
{
|
||||
u32 pmctrl;
|
||||
u8 reg8;
|
||||
int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc;
|
||||
em64t101_smm_state_save_area_t *state;
|
||||
|
||||
/* Emulate B2 register as the FADT / Linux expects it */
|
||||
|
|
@ -657,11 +631,10 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
|
|||
#endif
|
||||
}
|
||||
|
||||
tseg_relocate((void **)&mainboard_apmc);
|
||||
mainboard_apmc(reg8);
|
||||
mainboard_smi_apmc(reg8);
|
||||
}
|
||||
|
||||
static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
|
||||
static void southbridge_smi_pm1(void)
|
||||
{
|
||||
u16 pm1_sts;
|
||||
|
||||
|
|
@ -682,7 +655,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_
|
|||
}
|
||||
}
|
||||
|
||||
static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
|
||||
static void southbridge_smi_gpe0(void)
|
||||
{
|
||||
u32 gpe0_sts;
|
||||
|
||||
|
|
@ -690,17 +663,15 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state
|
|||
dump_gpe0_status(gpe0_sts);
|
||||
}
|
||||
|
||||
static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
|
||||
static void southbridge_smi_gpi(void)
|
||||
{
|
||||
void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi;
|
||||
u16 reg16;
|
||||
reg16 = inw(pmbase + ALT_GP_SMI_STS);
|
||||
outw(reg16, pmbase + ALT_GP_SMI_STS);
|
||||
|
||||
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
|
||||
|
||||
tseg_relocate((void **)&mainboard_gpi);
|
||||
mainboard_gpi(reg16);
|
||||
mainboard_smi_gpi(reg16);
|
||||
|
||||
if (reg16)
|
||||
printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
|
||||
|
|
@ -708,7 +679,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
|
|||
outw(reg16, pmbase + ALT_GP_SMI_STS);
|
||||
}
|
||||
|
||||
static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
|
||||
static void southbridge_smi_mc(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
|
@ -723,7 +694,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s
|
|||
|
||||
|
||||
|
||||
static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
|
||||
static void southbridge_smi_tco(void)
|
||||
{
|
||||
u32 tco_sts;
|
||||
|
||||
|
|
@ -760,7 +731,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
|
|||
}
|
||||
}
|
||||
|
||||
static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
|
||||
static void southbridge_smi_periodic(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
|
@ -773,7 +744,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s
|
|||
printk(BIOS_DEBUG, "Periodic SMI.\n");
|
||||
}
|
||||
|
||||
static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
|
||||
static void southbridge_smi_monitor(void)
|
||||
{
|
||||
#define IOTRAP(x) (trap_sts & (1 << x))
|
||||
u32 trap_sts, trap_cycle;
|
||||
|
|
@ -827,8 +798,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
|
|||
#undef IOTRAP
|
||||
}
|
||||
|
||||
typedef void (*smi_handler_t)(unsigned int node,
|
||||
smm_state_save_area_t *state_save);
|
||||
typedef void (*smi_handler_t)(void);
|
||||
|
||||
static smi_handler_t southbridge_smi[32] = {
|
||||
NULL, // [0] reserved
|
||||
|
|
@ -870,7 +840,7 @@ static smi_handler_t southbridge_smi[32] = {
|
|||
* @param node
|
||||
* @param state_save
|
||||
*/
|
||||
void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
|
||||
void southbridge_smi_handler(void)
|
||||
{
|
||||
int i, dump = 0;
|
||||
u32 smi_sts;
|
||||
|
|
@ -887,15 +857,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
|
|||
for (i = 0; i < 31; i++) {
|
||||
if (smi_sts & (1 << i)) {
|
||||
if (southbridge_smi[i]) {
|
||||
#if CONFIG_SMM_TSEG
|
||||
smi_handler_t handler = (smi_handler_t)
|
||||
((u8*)southbridge_smi[i] +
|
||||
smi_get_tseg_base());
|
||||
if (handler)
|
||||
handler(node, state_save);
|
||||
#else
|
||||
southbridge_smi[i](node, state_save);
|
||||
#endif
|
||||
southbridge_smi[i]();
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
|
||||
"handler available.\n", i);
|
||||
|
|
|
|||
Loading…
Reference in New Issue