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soc/intel/cmn: Clear interrupt status after HECI-1 has been received 

According to Intel doc#630774, BIOS should clear Host Interrupt Status
if it has read all the slots of the message from the ME circular buffer.
Since this is not found in client ME document, add a Kconfig
SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server
ME SKU.

On SPR-SP, if mainboard calls get_me_fw_version via HECI-1, with the
change can avoid seeing below Linux warning during boot with Linux
v5.12:
[   17.868929] irq 16: nobody cared (try booting with the "irqpoll" option)
[   17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0
[   17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1
[   17.922327] Call Trace:
[   17.927780]  <IRQ>
[   17.932253]  dump_stack+0x64/0x7c
[   17.939640]  __report_bad_irq+0x37/0xb1
[   17.948206]  note_interrupt.cold.11+0xa/0x63
[   17.957713]  handle_irq_event_percpu+0x6a/0x80
[   17.967626]  handle_irq_event+0x2a/0x50
[   17.976163]  handle_fasteoi_irq+0x9e/0x140
[   17.985305]  __common_interrupt+0x38/0x90
[   17.994255]  common_interrupt+0x7a/0xa0
[   18.002821]  </IRQ>
[   18.007514]  asm_common_interrupt+0x1e/0x40

Change-Id: I1cf21112870e53a11134d43e461b735ead239717
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
This commit is contained in:
Johnny Lin 2022-08-09 15:36:30 +08:00 committed by Martin L Roth
parent 5b89bf4666
commit a3e68c9f95
2 changed files with 8 additions and 0 deletions
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6
src/soc/intel/common/block/cse/Kconfig
View File

@ -73,6 +73,12 @@ config SOC_INTEL_CSE_LITE_SKU
help help
Enables CSE Lite SKU Enables CSE Lite SKU
config SOC_INTEL_CSE_SERVER_SKU
bool
default n
help
Enables CSE Server SKU
config SOC_INTEL_CSE_RW_UPDATE config SOC_INTEL_CSE_RW_UPDATE
bool "Enable the CSE RW Update Feature" bool "Enable the CSE RW Update Feature"
default n default n

2
src/soc/intel/common/block/cse/cse.c
View File

@ -572,6 +572,8 @@ static enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen)
if ((hdr & MEI_HDR_IS_COMPLETE) && received) { if ((hdr & MEI_HDR_IS_COMPLETE) && received) {
*maxlen = p - (uint8_t *)buff; *maxlen = p - (uint8_t *)buff;
if (CONFIG(SOC_INTEL_CSE_SERVER_SKU))
clear_int();
return CSE_TX_RX_SUCCESS; return CSE_TX_RX_SUCCESS;
} }
} }