Mainboard: Supermicro/h8qgi mainboard update

1. Supermicro H8QGI mainboard update to support both family10 Revison D processor and family15 model 00-0fh processor in one binary image. 2. RD890/SR56X0 IO hub CIMX wrapper support. 3. SP5100/SB700 southbridge CIMX wrapper support. Both 8 cores and 16 Cores InterLagos Opteron Processor are tested on this platform. Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested. Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/567 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-07 20:32:38 +08:00 · 2012-02-07 20:32:38 +08:00 · a3f060748b
parent c55f5a0e07
commit a3f060748b
28 changed files with 1461 additions and 532 deletions
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@ -22,13 +22,15 @@ if BOARD_SUPERMICRO_H8QGI
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_AGESA_FAMILY10
+	select CPU_AMD_AGESA_FAMILY15
-	select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX
+	select CPU_AMD_SOCKET_G34
-	select NORTHBRIDGE_AMD_AGESA_FAMILY10
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX
-	select SOUTHBRIDGE_AMD_SR5650
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15
-	select SOUTHBRIDGE_AMD_SP5100
+	select NORTHBRIDGE_AMD_CIMX_RD890
 	select SOUTHBRIDGE_AMD_CIMX_SB700
 	select SUPERIO_WINBOND_W83627DHG
 	select SUPERIO_NUVOTON_WPCM450
 	select UDELAY_TSC
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
@ -36,15 +38,11 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_MP_TABLE
 	select HAVE_HARD_RESET
 	select SERIAL_CPU_INIT
 	select AMDMCT
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_2048
 	select TINY_BOOTBLOCK
 	#select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict
 config AMD_AGESA
 	bool
 	default y
 config MAINBOARD_DIR
 	string
 	default supermicro/h8qgi
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@ -17,15 +17,29 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c
 romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
 romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
 romstage-y += buildOpts.c
 romstage-y += agesawrapper.c
 romstage-y += dimmSpd.c
 romstage-y += BiosCallOuts.c
 romstage-y += platform_oem.c
 ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
 ramstage-y += buildOpts.c
 ramstage-y += agesawrapper.c
 ramstage-y += dimmSpd.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += platform_oem.c
 AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
 CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
 AGESA_ROOT ?= $(AGESA_PREFIX)/f15
 NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890
 SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700
 subdirs-y += ../../../../$(AGESA_ROOT)
--- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
--- a/src/mainboard/supermicro/h8qgi/acpi/ide.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/ide.asl
--- a/src/mainboard/supermicro/h8qgi/acpi/routing.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
--- a/src/mainboard/supermicro/h8qgi/acpi/sata.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
--- a/src/mainboard/supermicro/h8qgi/acpi/usb.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
--- a/src/mainboard/supermicro/h8qgi/acpi_tables.c
+++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <arch/ioapic.h>
 #include <arch/io.h>
 #include <device/pci.h>
@ -48,7 +49,6 @@ static void dump_mem(u32 start, u32 end)
 #endif
 extern const unsigned char AmlCode[];
 extern const unsigned char AmlCode_ssdt[];
 unsigned long acpi_fill_mcfg(unsigned long current)
@ -134,6 +134,29 @@ unsigned long acpi_fill_srat(unsigned long current)
 	return current;
 }
 unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
 {
 	int lens;
 	msr_t msr;
 	char pscope[] = "\\_SB.PCI0";
 	lens = acpigen_write_scope(pscope);
 	msr = rdmsr(TOP_MEM);
 	lens += acpigen_write_name_dword("TOM1", msr.lo);
 	msr = rdmsr(TOP_MEM2);
 	/*
 	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
 	 * here.
 	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
 	 * slide 22ff.
 	 * Shift value right by 20 bit to make it fit into 32bit,
 	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
 	 */
 	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
 	acpigen_patch_len(lens - 1);
 	return (unsigned long) (acpigen_get_current());
 }
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
@ -146,7 +169,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_fadt_t *fadt;
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
-	//acpi_header_t *ssdt;
+	acpi_header_t *ssdt;
 	acpi_header_t *ssdt2;
 	acpi_header_t *alib;
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
@ -234,38 +259,38 @@ unsigned long write_acpi_tables(unsigned long start)
 	}
 	/* SSDT */
 	/* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */
 #ifdef UNUSED_CODE
 	current	 = (current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
 	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
 	if (alib != NULL) {
 		memcpy((void *)current, alib, alib->length);
 		ssdt = (acpi_header_t *) current;
 		current += alib->length;
 		acpi_add_table(rsdp,alib);
 	} else {
 		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
 	}
 #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
 	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
-		memcpy(current, ssdt, ssdt->length);
+		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
-	}
+	} else {
-	else {
+		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 		ssdt = (acpi_header_t *) current;
 		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
 		current += ssdt->length;
 		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
 		/* recalculate checksum */
 		ssdt->checksum = 0;
 		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
 	}
 	acpi_add_table(rsdp,ssdt);
 	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
 #endif
-	/* DSDT */
+	current	 = ( current + 0x0f) & -0x10;
-	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
-	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+	ssdt2 = (acpi_header_t *) current;
-	dsdt = (acpi_header_t *)current; // it will used by fadt
+	acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += ssdt2->length;
-	current += dsdt->length;
+	acpi_add_table(rsdp,ssdt2);
 	memcpy(dsdt, &AmlCode, dsdt->length);
 	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -34,7 +34,6 @@
 #include "Dispatcher.h"
 #include "cpuCacheInit.h"
 #include "amdlib.h"
 #include "platform_oem.h"
 #include "Filecode.h"
 #include "heapManager.h"
 #include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
@ -54,7 +53,7 @@ VOID *AcpiSlit    = NULL;
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;
-//VOID *AcpiAlib    = NULL;
+VOID *AcpiAlib    = NULL;
 /*----------------------------------------------------------------------------------------
@ -76,6 +75,7 @@ VOID *AcpiWheaCmc = NULL;
 *                          L O C A L    F U N C T I O N S
 *---------------------------------------------------------------------------------------
 */
 extern VOID OemCustomizeInitEarly(IN  OUT AMD_EARLY_PARAMS *InitEarly);
 static UINT32 agesawrapper_amdinitcpuio(VOID)
 {
@ -87,6 +87,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
 	UINT32			node;
 	UINT32			sblink;
 	UINT32			i;
 	UINT32			TOM;
 	/* get the number of coherent nodes in the system */
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
@ -130,12 +131,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
 		PciData = 0x00000A03;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		/* Set F0000000-FFFFFFFF to Node0 sbLink. */
+		/* Set TOM1-FFFFFFFF to Node0 sbLink. */
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
 		PciData = 0x00FFFF00;
 		PciData |= sblink << 4;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciData = 0x00F00000 | 0x03;
+		TOM = (UINT32)MsrRead(TOP_MEM);
 		PciData = (TOM >> 8) | 0x03;
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
@ -155,13 +157,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		/* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */
+		/* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink  and enabled VGA IO*/
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
-		PciData = 0x0000E000;
+		PciData = 0x00FFF000;
 		PciData |= sblink << 4;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
-		PciData = 0x00009033;
+		PciData = 0x00000033;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	}
@ -190,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID)
 	LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5;
+	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800;
+	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
 	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 	Status = AGESA_SUCCESS;
@ -223,7 +225,10 @@ UINT32 agesawrapper_amdinitreset(VOID)
 	AmdParamStruct.StdHeader.CalloutPtr = NULL;
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
 	if (status != AGESA_SUCCESS) {
 		return (UINT32)status;
 	}
 	AmdResetParams.HtConfig.Depth = 0;
 	//MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
@ -257,16 +262,19 @@ UINT32 agesawrapper_amdinitearly(VOID)
 	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
 	if (status != AGESA_SUCCESS) {
 		return (UINT32)status;
 	}
 	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
 	OemCustomizeInitEarly(AmdEarlyParamsPtr);
-	status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	status = AmdInitEarly(AmdEarlyParamsPtr);
 	if (status != AGESA_SUCCESS)
 		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
-	GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader);
+	GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
 	FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
 	printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
@ -280,6 +288,7 @@ UINT32 agesawrapper_amdinitpost(VOID)
 	UINT16 i;
 	UINT32 *HeadPtr;
 	AMD_INTERFACE_PARAMS  AmdParamStruct;
 	AMD_POST_PARAMS *PostParams;
 	BIOS_HEAP_MANAGER    *BiosManagerPtr;
 	UINT32 TscRateInMhz;
 	CPU_SPECIFIC_SERVICES *FamilySpecificServices;
@ -296,10 +305,15 @@ UINT32 agesawrapper_amdinitpost(VOID)
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
-	status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) {
-	if (status != AGESA_SUCCESS)
+		return (UINT32)status;
-		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+	}
 	PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
 	status = AmdInitPost(PostParams);
 	if (status != AGESA_SUCCESS) {
 		agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
 	}
 	AmdReleaseStruct(&AmdParamStruct);
 	/* Initialize heap space */
@ -313,7 +327,7 @@ UINT32 agesawrapper_amdinitpost(VOID)
 	BiosManagerPtr->StartOfAllocatedNodes = 0;
 	BiosManagerPtr->StartOfFreedNodes = 0;
-	GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader);
+	GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
 	FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
 	printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
@ -324,6 +338,7 @@ UINT32 agesawrapper_amdinitenv(VOID)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
 	AMD_ENV_PARAMS *EnvParams;
 	LibAmdMemFill(&AmdParamStruct,
 			0,
@ -336,10 +351,15 @@ UINT32 agesawrapper_amdinitenv(VOID)
 	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
+
-	status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+	status = AmdCreateStruct(&AmdParamStruct);
 	if (status != AGESA_SUCCESS) {
 		return (UINT32)status;
 	}
 	EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
 	status = AmdInitEnv(EnvParams);
 	if (status != AGESA_SUCCESS)
-		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+		agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus);
 	AmdReleaseStruct(&AmdParamStruct);
 	return (UINT32)status;
@ -363,10 +383,8 @@ VOID * agesawrapper_getlateinitptr(int pick)
 			return AcpiWheaMce;
 		case PICK_WHEA_CMC:
 			return AcpiWheaCmc;
 /*
 		case PICK_ALIB:
 			return AcpiAlib;
 */
 		default:
 			return NULL;
 	}
@ -394,7 +412,10 @@ UINT32 agesawrapper_amdinitmid(VOID)
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
 	if (status != AGESA_SUCCESS) {
 		return (UINT32)status;
 	}
 	status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
 	if (status != AGESA_SUCCESS)
 		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
@ -406,33 +427,48 @@ UINT32 agesawrapper_amdinitmid(VOID)
 UINT32 agesawrapper_amdinitlate(VOID)
 {
 	AGESA_STATUS		Status;
-	AMD_LATE_PARAMS AmdLateParams;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
 	AMD_LATE_PARAMS		*AmdLateParamsPtr;
-	LibAmdMemFill(&AmdLateParams,
+	LibAmdMemFill(&AmdParamStruct,
 		       0,
-			sizeof(AMD_LATE_PARAMS),
+		       sizeof (AMD_INTERFACE_PARAMS),
-			&(AmdLateParams.StdHeader));
+		       &(AmdParamStruct.StdHeader));
-	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
-	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.AllocationMethod = PostMemDram;
-	AmdLateParams.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-	AmdLateParams.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-	AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	Status = AmdInitLate(&AmdLateParams);
+	AmdCreateStruct (&AmdParamStruct);
 	AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
 	printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
 	Status = AmdInitLate(AmdLateParamsPtr);
 	if (Status != AGESA_SUCCESS) {
-		agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
+		agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus);
 		ASSERT(Status == AGESA_SUCCESS);
 	}
 	DmiTable    = AmdLateParamsPtr->DmiTable;
 	AcpiPstate  = AmdLateParamsPtr->AcpiPState;
 	AcpiSrat    = AmdLateParamsPtr->AcpiSrat;
 	AcpiSlit    = AmdLateParamsPtr->AcpiSlit;
 	AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
 	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
 	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
-	DmiTable       = AmdLateParams.DmiTable;
+	printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
-	AcpiPstate     = AmdLateParams.AcpiPState;
+		"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
-	AcpiSrat       = AmdLateParams.AcpiSrat;
+		"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
-	AcpiSlit       = AmdLateParams.AcpiSlit;
+		 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
 		 AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
-	AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
+	/* Don't release the structure until coreboot has copied the ACPI tables.
-	AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
+	 * AmdReleaseStruct (&AmdLateParams);
-	//AcpiAlib       = AmdLateParams.AcpiAlib;
+	 */
 	return (UINT32)Status;
 }
@ -464,15 +500,6 @@ UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr)
 		ASSERT(Status <= AGESA_UNSUPPORTED);
 	}
 	DmiTable       = AmdLateParams.DmiTable;
 	AcpiPstate     = AmdLateParams.AcpiPState;
 	AcpiSrat       = AmdLateParams.AcpiSrat;
 	AcpiSlit       = AmdLateParams.AcpiSlit;
 	AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
 	AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
 	//  AcpiAlib       = AmdLateParams.AcpiAlib;
 	return (UINT32)Status;
 }
@ -784,10 +811,6 @@ static void agesa_error(EVENT_PARAMS *event)
 			printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n");
 			break;
 		case MEM_ERROR_ECC_DIS:
 			printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n");
 			break;
 		case MEM_ERROR_DIMM_SPARING_NOT_ENABLED:
 			printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n");
 			break;
@ -1141,6 +1164,7 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event)
 */
 UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
 {
 	printk(BIOS_DEBUG, "enter in %s\n", __func__);
 	AGESA_STATUS Status;
 	EVENT_PARAMS AmdEventParams;
@ -1164,6 +1188,7 @@ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
 		Status = AmdReadEventLog(&AmdEventParams);
 	}
 	printk(BIOS_DEBUG, "exit %s \n", __func__);
 	return (UINT32)Status;
 }
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -70,7 +70,10 @@
 ////#define BLDOPT_REMOVE_SLIT                     TRUE
 //#define BLDOPT_REMOVE_WHEA                     TRUE
 //#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
+
 /*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */
 #define BLDOPT_REMOVE_EARLY_SAMPLES		FALSE
 //#define BLDOPT_REMOVE_HT_ASSIST                TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E            TRUE
 //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
@ -107,7 +110,7 @@
 #define BLDCFG_ONLINE_SPARE                       FALSE
 #define BLDCFG_BANK_SWIZZLE                       TRUE
 #define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR800_FREQUENCY
+#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1333_FREQUENCY //DDR800_FREQUENCY
 #define BLDCFG_DQS_TRAINING_CONTROL               TRUE
 #define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
 #define BLDCFG_USE_BURST_MODE                     FALSE
@ -297,6 +300,27 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] =
 	{0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 	{0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 	{1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 	{1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
 	{1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
 	{1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
 	{1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 	{1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 	{2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 	{2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
 	{2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
 	{2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
 	{2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 	{2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 	{3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 	{3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
 	{3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
 	{3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
 	{3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 	{3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 	/* Coherent link deemphasis. */
 	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
@ -373,22 +397,21 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] =
 	{HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
 	{HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
 	{HT_SOCKET3, HT_LINK3B, HT_SOCKET2},
 };
 CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 {
-	{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull},
+	{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E},
-	{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull},
+	{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E},
-	{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull},
+	{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000ull},
+	{AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000ull},
+	{AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000ull},
+	{AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000ull},
+	{AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818ull},
+	{AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818ull},
+	{AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818ull},
+	{AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818ull},
+	{AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818},
 	{CPU_LIST_TERMINAL}
 };
@ -403,7 +426,7 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 /*  Process the options...
 * This file include MUST occur AFTER the user option selection settings
 */
-#define AGESA_ENTRY_INIT_RESET                    FALSE//TRUE
+#define AGESA_ENTRY_INIT_RESET                    TRUE//FALSE
 #define AGESA_ENTRY_INIT_RECOVERY                 FALSE
 #define AGESA_ENTRY_INIT_EARLY                    TRUE
 #define AGESA_ENTRY_INIT_POST                     TRUE
@ -415,7 +438,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
-#include "GnbInterface.h"     /*prototype for GnbInterfaceStub*/
+/*
 #if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1)
  #define BLDOPT_REMOVE_FAMILY_10_SUPPORT         TRUE
 #endif
 #if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1)
  #define BLDOPT_REMOVE_FAMILY_15_SUPPORT         TRUE
 #endif
 */
 //#include "GnbInterface.h"     /*prototype for GnbInterfaceStub*/
 #include "MaranelloInstall.h"
 /*----------------------------------------------------------------------------------------
@ -423,6 +455,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 *----------------------------------------------------------------------------------------
 */
 //reference BKDG Table87: works
 #define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
 #define SEED_A 0x54
 #define SEED_B 0x4D
 #define SEED_C 0x45
 #define SEED_D 0x40
 #define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
 //4B 41 51
 /*
 *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
@ -486,6 +528,40 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 	//      Byte6Seed, Byte7Seed, ByteEccSeed)
 	//      Specifies the write leveling seed for a channel of a socket.
 	//
 	/* Specifies the write leveling seed for a channel of a socket.
 	 * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID,
 	 *                     Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
 	 *                     Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed,
 	 *                     ByteEccSeed)
 	 */
 	WRITE_LEVELING_SEED(
 			ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
 			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
 			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
 			F15_WL_SEED),
 	/* HW_RXEN_SEED(SocketID, ChannelID, DimmID,
 	 *              Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
 	 *              Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed)
 	 */
 	HW_RXEN_SEED(
 		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
 		SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
 		SEED_A),
 	HW_RXEN_SEED(
 		ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
 		SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
 		SEED_B),
 	HW_RXEN_SEED(
 		ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
 		SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
 		SEED_C),
 	HW_RXEN_SEED(
 		ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
 		SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
 		SEED_D),
 	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
 	PSO_END
 };
@ -493,7 +569,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 /*
 * These tables are optional and may be used to adjust memory timing settings
 */
 //HY Customer table
 UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] =
 {
--- a/src/mainboard/supermicro/h8qgi/cmos.layout
+++ b/src/mainboard/supermicro/h8qgi/cmos.layout
--- a/src/mainboard/supermicro/h8qgi/devicetree.cb
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@ -16,20 +16,18 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
-chip northbridge/amd/agesa/family10/root_complex
+chip northbridge/amd/agesa/family15/root_complex
 	device lapic_cluster 0 on
-		chip cpu/amd/agesa/family10
+		chip cpu/amd/agesa/family15
-			device lapic 0x10 on end
+			device lapic 0x20 on end #f15
 			#device lapic 0x10 on end #f10
 		end
 	end
 	device pci_domain 0 on
 		subsystemid 0x15d9 0xab11 inherit #SuperMicro
-		chip northbridge/amd/agesa/family10 # CPU side of HT root complex
+		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-			device pci 18.0 on end # link 0
+			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology
-			device pci 18.0 on end # link 1
+				chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex
 			device pci 18.0 on end # link 2
 			device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3
 				chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex
 					device pci 0.0 on  end # HT Root Complex 0x9600
 					device pci 0.1 off end # CLKCONFIG
 					device pci 2.0 on  end # GPP1 Port0  x16 SLOT4, 0x5A16
@ -46,11 +44,10 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
 					register "gpp1_configuration" = "0"   # Configuration 16:0 default
 					register "gpp2_configuration" = "1"   # Configuration 8:8
-					register "gpp3a_configuration" = "2"   # Configuration 4:1:1:0:0:0
+					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
 					#register "gpp3a_configuration" = "11"   # Configuration 1:1:1:1:1:1
 					register "port_enable" = "0x2104"
-				end #southbridge/amd/sr5650
+				end #northbridge/amd/cimx/rd890
-				chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus
+				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus
 					device pci 11.0 on end # SATA
 					device pci 12.0 on end # USB1
 					device pci 12.1 on end # USB1
@ -59,8 +56,8 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci 13.1 on end # USB2
 					device pci 13.2 on end # USB2
 					device pci 14.0 on end # SM
-					device pci 14.1 on end # IDE  0x439c
+					device pci 14.1 off end # IDE  0x439c
-					device pci 14.2 off end # HDA  0x4383, h8qgi doesnt have codec.
+					device pci 14.2 off end # HDA  0x4383, h8qgi not have codec.
 					device pci 14.3 on # LPC  0x439d
 						chip superio/winbond/w83627dhg
 							device pnp 2e.0 off #  Floppy
@ -113,64 +110,15 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 3
 					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-				end # southbridge/amd/sp5100
+				end # southbridge/amd/cimx/sb700
 			end # device pci 18.0
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 			device pci 18.4 on end
-
+			device pci 18.5 on end #f15
-			device pci 19.0 on end
+		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
 			device pci 19.1 on end
 			device pci 19.2 on end
 			device pci 19.3 on end
 			device pci 19.4 on end
 			device pci 1a.0 on end
 			device pci 1a.0 on end
 			device pci 1a.0 on end
 			device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3
 			end
 			device pci 1a.1 on end
 			device pci 1a.2 on end
 			device pci 1a.3 on end
 			device pci 1a.4 on end
 			device pci 1b.0 on end
 			device pci 1b.1 on end
 			device pci 1b.2 on end
 			device pci 1b.3 on end
 			device pci 1b.4 on end
 			device pci 1c.0 on end
 			device pci 1c.1 on end
 			device pci 1c.2 on end
 			device pci 1c.3 on end
 			device pci 1c.4 on end
 			device pci 1d.0 on end
 			device pci 1d.1 on end
 			device pci 1d.2 on end
 			device pci 1d.3 on end
 			device pci 1d.4 on end
 			device pci 1e.0 on end
 			device pci 1e.1 on end
 			device pci 1e.2 on end
 			device pci 1e.3 on end
 			device pci 1e.4 on end
 			device pci 1f.0 on end
 			device pci 1f.1 on end
 			device pci 1f.2 on end
 			device pci 1f.3 on end
 			device pci 1f.4 on end
 		end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex
 	end #pci_domain
-end #northbridge/amd/agesa/family10/root_complex
+end #northbridge/amd/agesa/family15/root_complex
--- a/src/mainboard/supermicro/h8qgi/dimmSpd.c
+++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -35,17 +35,27 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 * @param reg -GPIO Cntrl Register
 * @param out -GPIO bitmap
 * @param out -GPIO enable bitmap
 * @return  old setting
 */
-static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
+static u8 sp5100_set_gpio(u8 reg, u8 out, u8 enable)
 {
-        u8 value;
+	u8 value, ret;
 	device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
 	value = pci_read_config8(sm_dev, reg);
 	ret = value;
 	value &= ~(enable);
 	value |= out;
 	value &= ~(enable << 4);
 	pci_write_config8(sm_dev, reg, value);
 	return ret;
 }
 static void sp5100_restore_gpio(u8 reg, u8 value)
 {
 	device_t sm_dev = PCI_DEV(0, 0x14, 0);
 	pci_write_config8(sm_dev, reg, value);
 }
 /*-----------------------------------------------------------------------------
@ -55,31 +65,31 @@ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
 static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm
 	/* socket 0 */
 	{
-		{0xAE, 0xAC},
+		{0xAC, 0xAE},
-		{0xAA, 0xA8},
+		{0xA8, 0xAA},
-		{0xA6, 0xA4},
+		{0xA4, 0xA6},
-		{0xA2, 0xA0},
+		{0xA0, 0xA2},
 	},
 	/* socket 1 */
 	{
-		{0xAE, 0xAC},
+		{0xAC, 0xAE},
-		{0xAA, 0xA8},
+		{0xA8, 0xAA},
-		{0xA6, 0xA4},
+		{0xA4, 0xA6},
-		{0xA2, 0xA0},
+		{0xA0, 0xA2},
 	},
 	/* socket 2 */
 	{
-		{0xAE, 0xAC},
+		{0xAC, 0xAE},
-		{0xAA, 0xA8},
+		{0xA8, 0xAA},
-		{0xA6, 0xA4},
+		{0xA4, 0xA6},
-		{0xA2, 0xA0},
+		{0xA0, 0xA2},
 	},
 	/* socket 3 */
 	{
-		{0xAE, 0xAC},
+		{0xAC, 0xAE},
-		{0xAA, 0xA8},
+		{0xA8, 0xAA},
-		{0xA6, 0xA4},
+		{0xA4, 0xA6},
-		{0xA2, 0xA0},
+		{0xA0, 0xA2},
 	},
 };
@ -177,25 +187,17 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
 	return 0;
 }
 static void writePmReg (int reg, int data)
 {
 	outb(reg, 0xCD6);
 	outb(data, 0xCD7);
 }
 static void setupFch (int ioBase)
 {
-	writePmReg (0x2D, ioBase >> 8);
+	outb(66000000 / 400000 / 4, ioBase + 0x0E); /* set SMBus clock to 400 KHz */
 	writePmReg (0x2C, ioBase | 1);
 	writePmReg (0x29, 0x80);
 	writePmReg (0x28, 0x61);
 	outb(66000000 / 400000 / 4, ioBase + 0x0E); // set SMBus clock to 400 KHz
 }
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
 {
 	AGESA_STATUS status;
 	int spdAddress, ioBase;
 	u8 i2c_channel;
 	u8 backup;
 	device_t sm_dev;
 	if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
@ -211,7 +213,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 	 *   1  0   channel 3 (Socket3)
 	 *   1  1   channel 4 (Socket4)
 	 */
-	sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03);
+	backup = sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03);
 	spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
 	if (spdAddress == 0)
@ -219,11 +221,14 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 	/*
 	 * SMBus Base Address was set during southbridge early setup.
-	 * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000
+	 * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000, CIMX using 0xB00 as default
 	 */
 	sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0);
 	ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0);
 	setupFch(ioBase);
-	return readspd(ioBase, spdAddress, (void *)info->Buffer, 256);
+	status = readspd(ioBase, spdAddress, (void *)info->Buffer, 256);
 	sp5100_restore_gpio(SP5100_GPIO53_56, backup);
 	return status;
 }
--- a/src/mainboard/supermicro/h8qgi/dsdt.asl
+++ b/src/mainboard/supermicro/h8qgi/dsdt.asl
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -988,73 +988,58 @@ DefinitionBlock (
 	Scope(\_GPE) {	/* Start Scope GPE */
 		/*  General event 0  */
-		/* Method(_L00) {
+		Method(_L00) {
-		*	DBGO("\\_GPE\\_L00\n")
+		      //DBGO("\\_GPE\\_L00\n")
-		* }
+		}
 		*/
 		/*  General event 1  */
-		/* Method(_L01) {
+		Method(_L01) {
-		*	DBGO("\\_GPE\\_L00\n")
+		      //DBGO("\\_GPE\\_L01\n")
-		* }
+		}
 		*/
 		/*  General event 2  */
-		/* Method(_L02) {
+		Method(_L02) {
-		*	DBGO("\\_GPE\\_L00\n")
+		      //DBGO("\\_GPE\\_L02\n")
-		* }
+		}
 		*/
 		/*  General event 3  */
 		Method(_L03) {
-			/* DBGO("\\_GPE\\_L00\n") */
+			//DBGO("\\_GPE\\_L00\n")
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
 		/*  General event 4  */
-		/* Method(_L04) {
+		Method(_L04) {
-		*	DBGO("\\_GPE\\_L00\n")
+		      //DBGO("\\_GPE\\_L04\n")
-		* }
+		}
 		*/
 		/*  General event 5  */
-		/* Method(_L05) {
+		Method(_L05) {
-		*	DBGO("\\_GPE\\_L00\n")
+		      //DBGO("\\_GPE\\_L05\n")
-		* }
+		}
 		*/
-		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* _L06 General event 6 - Used for GPM6, moved to USB.asl */
-		/* Method(_L06) {
+		/* _L07 General event 7 - Used for GPM7, moved to USB.asl */
 		*	DBGO("\\_GPE\\_L00\n")
 		* }
 		*/
 		/*  General event 7 - Used for GPM7, moved to USB.asl */
 		/* Method(_L07) {
 		*	DBGO("\\_GPE\\_L07\n")
 		* }
 		*/
 		/*  Legacy PM event  */
 		Method(_L08) {
-			/* DBGO("\\_GPE\\_L08\n") */
+			//DBGO("\\_GPE\\_L08\n")
 		}
 		/*  Temp warning (TWarn) event  */
 		Method(_L09) {
-			/* DBGO("\\_GPE\\_L09\n") */
+			//DBGO("\\_GPE\\_L09\n")
 			Notify (\_TZ.TZ00, 0x80)
 		}
 		/*  Reserved  */
-		/* Method(_L0A) {
+		Method(_L0A) {
-		*	DBGO("\\_GPE\\_L0A\n")
+		      //DBGO("\\_GPE\\_L0A\n")
-		* }
+		}
 		*/
 		/*  USB controller PME#  */
 		Method(_L0B) {
-			/* DBGO("\\_GPE\\_L0B\n") */
+			//DBGO("\\_GPE\\_L0B\n")
 			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
@ -1065,126 +1050,81 @@ DefinitionBlock (
 		}
 		/*  AC97 controller PME#  */
-		/* Method(_L0C) {
+		Method(_L0C) {
-		*	DBGO("\\_GPE\\_L0C\n")
+		      //DBGO("\\_GPE\\_L0C\n")
-		* }
+		}
 		*/
 		/*  OtherTherm PME#  */
-		/* Method(_L0D) {
+		Method(_L0D) {
-		*	DBGO("\\_GPE\\_L0D\n")
+		      //DBGO("\\_GPE\\_L0D\n")
-		* }
+		}
 		*/
-		/*  GPM9 SCI event - Moved to USB.asl */
+		/* _L0E GPM9 SCI event - Moved to USB.asl */
 		/* Method(_L0E) {
 		*	DBGO("\\_GPE\\_L0E\n")
 		* }
 		*/
 		/*  PCIe HotPlug event  */
-		/* Method(_L0F) {
+		Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
+			//DBGO("\\_GPE\\_L0F\n")
-		* }
+		}
 		*/
 		/*  ExtEvent0 SCI event  */
 		Method(_L10) {
-			/* DBGO("\\_GPE\\_L10\n") */
+			//DBGO("\\_GPE\\_L10\n")
 		}
 		/*  ExtEvent1 SCI event  */
 		Method(_L11) {
-			/* DBGO("\\_GPE\\_L11\n") */
+			//DBGO("\\_GPE\\_L11\n")
 		}
 		/*  PCIe PME# event  */
-		/* Method(_L12) {
+		Method(_L12) {
-		*	DBGO("\\_GPE\\_L12\n")
+		      //DBGO("\\_GPE\\_L12\n")
-		* }
+		}
 		*/
-		/*  GPM0 SCI event - Moved to USB.asl */
+		/* _L13 GPM0 SCI event - Moved to USB.asl */
-		/* Method(_L13) {
+		/* _L14 GPM1 SCI event - Moved to USB.asl */
-		* 	DBGO("\\_GPE\\_L13\n")
+		/* _L15 GPM2 SCI event - Moved to USB.asl */
-		* }
+		/* _L16 GPM3 SCI event - Moved to USB.asl */
-		*/
+		/* _L17 GPM8 SCI event - Moved to USB.asl */
 		/*  GPM1 SCI event - Moved to USB.asl */
 		/* Method(_L14) {
 		* 	DBGO("\\_GPE\\_L14\n")
 		* }
 		*/
 		/*  GPM2 SCI event - Moved to USB.asl */
 		/* Method(_L15) {
 		* 	DBGO("\\_GPE\\_L15\n")
 		* }
 		*/
 		/*  GPM3 SCI event - Moved to USB.asl */
 		/* Method(_L16) {
 		*	DBGO("\\_GPE\\_L16\n")
 		* }
 		*/
 		/*  GPM8 SCI event - Moved to USB.asl */
 		/* Method(_L17) {
 		* 	DBGO("\\_GPE\\_L17\n")
 		* }
 		*/
 		/*  GPIO0 or GEvent8 event  */
 		Method(_L18) {
-			/* DBGO("\\_GPE\\_L18\n") */
+			//DBGO("\\_GPE\\_L18\n")
 			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
-		/*  GPM4 SCI event - Moved to USB.asl */
+		/* _L19 GPM4 SCI event - Moved to USB.asl */
-		/* Method(_L19) {
+		/* _L1A GPM5 SCI event - Moved to USB.asl */
 		* 	DBGO("\\_GPE\\_L19\n")
 		* }
 		*/
 		/*  GPM5 SCI event - Moved to USB.asl */
 		/* Method(_L1A) {
 		*	DBGO("\\_GPE\\_L1A\n")
 		* }
 		*/
 		/*  Azalia SCI event  */
 		Method(_L1B) {
-			/* DBGO("\\_GPE\\_L1B\n") */
+			//DBGO("\\_GPE\\_L1B\n")
 			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
 		/*  GPM6 SCI event - Reassigned to _L06 */
-		/* Method(_L1C) {
+		Method(_L1C) {
-		*	DBGO("\\_GPE\\_L1C\n")
+		      //DBGO("\\_GPE\\_L1C\n")
-		* }
+		}
 		*/
 		/*  GPM7 SCI event - Reassigned to _L07 */
-		/* Method(_L1D) {
+		Method(_L1D) {
-		*	DBGO("\\_GPE\\_L1D\n")
+		      //DBGO("\\_GPE\\_L1D\n")
-		* }
+		}
 		*/
 		/*  GPIO2 or GPIO66 SCI event  */
-		/* Method(_L1E) {
+		Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
+			//DBGO("\\_GPE\\_L1E\n")
-		* }
+		}
 		*/
-		/*  SATA SCI event - Moved to sata.asl */
+		/* _L1F SATA SCI event - Moved to sata.asl */
 		/* Method(_L1F) {
 		*	 DBGO("\\_GPE\\_L1F\n")
 		* }
 		*/
 	} 	/* End Scope GPE */
@ -1602,10 +1542,10 @@ DefinitionBlock (
 					,, , TypeStatic)
 				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 					0x0000,             // Granularity
-					0x9000,             // Range Minimum
+					0x0D00,             // Range Minimum
-					0xefff,             // Range Maximum
+					0xFFFF,             // Range Maximum
 					0x0000,             // Translation Offset
-					0x6000,             // Length
+					0xF300,             // Length
 					,, , TypeStatic)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	// VGA memory space
@ -1613,21 +1553,26 @@ DefinitionBlock (
 						0xE0000000,         // Address Base
 						0x10000000,         // Address Length, (1MB each Bus, 256 Buses by default)
 						MMIO)
 				DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
 						0x00000000,         // Granularity
 						0xF0000000,         // Range Minimum
 						0xFFFFFFFF,         // Range Maximum
 						0x00000000,         // Translation Offset
 						0x10000000,         // Length
 						,, , AddressRangeMemory, TypeStatic)
 			})
 			Method (_CRS, 0, NotSerialized)
 			{
 				CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
 				CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
-				Store (PCBA, BAS1)
+
-				Store (PCLN, LEN1)
+                                /*
                                 * Declare memory between TOM1 and 4GB as available
                                 * for PCI MMIO.
                                 * Use ShiftLeft to avoid 64bit constant (for XP).
                                 * This will work even if the OS does 32bit arithmetic, as
                                 * 32bit (0x00000000 - TOM1) will wrap and give the same
                                 * result as 64bit (0x100000000 - TOM1).
                                 */
 				Store(TOM1, BAS1)
                                ShiftLeft(0x10000000, 4, Local0)
                                Subtract(Local0, TOM1, Local0)
                                Store(Local0, LEN1)
 				//DBGO(TOM1)
 				Return (CRS)
 			}
--- a/src/mainboard/supermicro/h8qgi/fadt.c
+++ b/src/mainboard/supermicro/h8qgi/fadt.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -28,21 +28,17 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/device.h>
-#include "southbridge/amd/sb700/sb700.h"
+#include "Platform.h" /*sb700 platform header*/
-u16 pm_base = SB700_ACPI_IO_BASE;
+#ifndef ACPI_BLK_BASE
-/* pm_base should be set in sb acpi */
+  #define ACPI_BLK_BASE	PM1_EVT_BLK_ADDRESS
-/* pm_base should be got from bar2 of sb700. Here I compact ACPI
+#endif
 * registers into 32 bytes limit.
 * */
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	pm_base &= 0xFFFF;
+	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
 	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
@ -65,38 +61,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->s4bios_req = 0x0;
 	fadt->pstate_cnt = 0xe2;
 	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
 	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
 	pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
 	pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
 	pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
 	pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
 	pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
 	pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
 	/* CpuControl is in \_PR.CPU0, 6 bytes */
 	pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF);
 	pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8);
 	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
 	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
 	pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
 	pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
 	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
 						      * the contents of the PM registers at
 						      * index 60-6B to decode ACPI I/O address.
 						      * AcpiSmiEn & SmiCmdEn*/
 	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
+	outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
-	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
 	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
 	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
-	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
 	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
 	fadt->pm1_evt_len = 4;
@ -139,7 +112,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm1a_evt_blk.bit_width = 32;
 	fadt->x_pm1a_evt_blk.bit_offset = 0;
 	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
 	fadt->x_pm1a_evt_blk.addrh = 0x0;
 	fadt->x_pm1b_evt_blk.space_id = 1;
@ -154,7 +127,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm1a_cnt_blk.bit_width = 16;
 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
 	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
 	fadt->x_pm1b_cnt_blk.space_id = 1;
@ -169,7 +142,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm2_cnt_blk.bit_width = 0;
 	fadt->x_pm2_cnt_blk.bit_offset = 0;
 	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
 	fadt->x_pm2_cnt_blk.addrh = 0x0;
@ -177,7 +150,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm_tmr_blk.bit_width = 32;
 	fadt->x_pm_tmr_blk.bit_offset = 0;
 	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
@ -185,7 +158,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_gpe0_blk.bit_width = 32;
 	fadt->x_gpe0_blk.bit_offset = 0;
 	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
 	fadt->x_gpe0_blk.addrh = 0x0;
--- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -23,8 +23,10 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
 #include <cpu/amd/amdfam10_sysconf.h>
 #include "agesawrapper.h"
 #if CONFIG_AMD_SB_CIMX
 #include <sb_cimx.h>
 #endif
 /* Global variables for MB layouts and these will be shared by irqtable mptable
@ -34,22 +36,6 @@ u8 bus_isa;
 u8 bus_sp5100[2];
 u8 bus_sr5650[14];
 /*
 * Here you only need to set value in pci1234 for HT-IO that could be installed or not
 * You may need to preset pci1234 for HTIO board,
 * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
 */
 u32 pci1234x[] = {
 	0x0000ff0,
 };
 /*
 * HT Chain device num, actually it is unit id base of every ht device in chain,
 * assume every chain only have 4 ht device at most
 */
 u32 hcdnx[] = {
 	0x20202020,
 };
 u32 bus_type[256];
@ -106,8 +92,7 @@ void get_bus_conf(void)
 	bus_type[0] = 1;  /* pci */
-	bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff;
+	bus_sr5650[0] = 0;
 	//  bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 	bus_sp5100[0] = bus_sr5650[0];
 	/* sp5100 */
@ -151,4 +136,9 @@ void get_bus_conf(void)
 	/* I/O APICs:   APIC ID Version State   Address */
 	bus_isa = 10;
 #if CONFIG_AMD_SB_CIMX
 	sb_After_Pci_Init();
 	sb_Late_Post();
 #endif
 }
--- a/src/mainboard/supermicro/h8qgi/irq_tables.c
+++ b/src/mainboard/supermicro/h8qgi/irq_tables.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
--- a/src/mainboard/supermicro/h8qgi/mainboard.c
+++ b/src/mainboard/supermicro/h8qgi/mainboard.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -25,30 +25,42 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
-#include "southbridge/amd/sr5650/cmn.h"
+#include <NbPlatform.h>
 #include "chip.h"
-void set_pcie_dereset(void);
+void set_pcie_dereset(void *nbconfig);
-void set_pcie_reset(void);
+void set_pcie_reset(void *nbconfig);
 /**
 *
 */
-void set_pcie_reset(void)
+void set_pcie_reset(void *nbconfig)
 {
 }
 /**
 * Mainboard specific RD890 CIMx callback
 * Release Resets to PCIe Links
- * PCIE_RESET_GPIO1,2,4,5
+ * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie
 */
-void set_pcie_dereset(void)
+void set_pcie_dereset(void *nbconfig)
 {
-	device_t pcie_core_dev;
+	//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
 	u32 i;
 	u32 val;
 	u32 nb_addr;
-	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	val = 0x00000007UL;
-	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707);
+	AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
-	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007);
+	for (i = 0; i < MAX_NB_COUNT; i ++) {
 		nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
 		LibNbPciIndexRMW(nb_addr,
 				NB_HTIU_REGA8,
 				AccessS3SaveWidth32,
 				~val,
 				val,
 				 &(pConfig->Northbridges[i]));
 	}
 }
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -33,17 +33,16 @@ extern u8 bus_sp5100[2];
 extern u32 bus_type[256];
 extern u32 sbdn_sr5650;
 extern u32 sbdn_sp5100;
 extern u8 bus_isa;
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
 	int bus_isa;
 	u32 apicid_sp5100;
 	u32 apicid_sr5650;
 	device_t dev;
 	u32 dword;
 	u8 byte;
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	mptable_init(mc, LAPIC_ADDR);
@ -62,17 +61,18 @@ static void *smp_write_config_table(void *v)
 #if CONFIG_MAX_CPUS >= 16
 	apicid_sp5100 = 0x0;
 #else
-	apicid_sp5100 = CONFIG_MAX_CPUS + 1;
+	apicid_sp5100 = CONFIG_MAX_CPUS + 1
 #endif
 	apicid_sr5650 = apicid_sp5100 + 1;
 	//bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
 	dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
 	if (dev) {
 		/* Set SP5100 IOAPIC ID */
 		dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
 		smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
 #ifdef UNUSED_CODE
 		u8 byte;
 		/* Initialize interrupt mapping */
 		/* aza */
 		byte = pci_read_config8(dev, 0x63);
@ -85,6 +85,7 @@ static void *smp_write_config_table(void *v)
 		dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
 		/* dword |= 1<<22; PIC and APIC co exists */
 		pci_write_config32(dev, 0xAC, dword);
 #endif
 		/*
 		 * 00:12.0: PROG SATA : INT F
--- a/src/mainboard/supermicro/h8qgi/platform_cfg.h
+++ b/src/mainboard/supermicro/h8qgi/platform_cfg.h
@ -0,0 +1,54 @@
 /*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 #ifndef _PLATFORM_CFG_H_
 #define _PLATFORM_CFG_H_
 /* northbridge customize options */
 /**
 * Max number of northbridges in the system
 */
 #define MAX_NB_COUNT		1 //TODO: only 1 NB tested
 /**
 *  Enable check for PCIe endpoint to be ready for PCI enumeration.
 *
 */
 //#define  EPREADY_WORKAROUND_DISABLED
 /**
 *  Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
 *
 */
 #define  IOMMU_SUPPORT_DISABLE //TODO: enable it
 /**
 *  Disable server PCIe hotplug support.
 */
 //#define HOTPLUG_SUPPORT_DISABLED
 /**
 *  Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
 */
 //#define DEVICE_REMAP_DISABLE
 #endif //_PLATFORM_CFG_H_
--- a/src/mainboard/supermicro/h8qgi/platform_oem.c
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -21,7 +21,6 @@
 #include "amdlib.h"
 #include "Ids.h"
 #include "heapManager.h"
 #include "platform_oem.h"
 #include "Filecode.h"
 #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
@ -43,6 +42,7 @@
 *
 **/
 /*---------------------------------------------------------------------------------------*/
 VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
 VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
 {
 	//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
--- a/src/mainboard/supermicro/h8qgi/platform_oem.h
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.h
@ -1,29 +0,0 @@
 /*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2011 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 #ifndef _PLATFORM_OEM_H_
 #define _PLATFORM_OEM_H_
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
 VOID OemCustomizeInitEarly(IN  OUT AMD_EARLY_PARAMS *InitEarly);
 #endif //_PLATFORM_OEM_H_
--- a/src/mainboard/supermicro/h8qgi/rd890_cfg.c
+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c
@ -0,0 +1,274 @@
 /*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 #include "NbPlatform.h"
 #include "rd890_cfg.h"
 #include "northbridge/amd/cimx/rd890/chip.h"
 #include "nbInitializer.h"
 #include <string.h>
 #include <arch/ioapic.h>
 #ifndef __PRE_RAM__
 #include <device/device.h>
 extern void set_pcie_reset(void *config);
 extern void set_pcie_dereset(void *config);
 /**
 * Platform dependent configuration at ramstage
 */
 static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
 {
 	u16 i;
 	PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
 	//AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
 	struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
 	DEFAULT_PLATFORM_CONFIG(platform_config);
 	/* update the platform depentent configuration by devicetree */
 	rd890_info  = nb_dev->chip_info;
 	platform_config.PortEnableMap = rd890_info->port_enable;
 	if (rd890_info->gpp1_configuration == 0) {
 		platform_config.Gpp1Config = GFX_CONFIG_AAAA;
 	} else if (rd890_info->gpp1_configuration == 1) {
 		platform_config.Gpp1Config = GFX_CONFIG_AABB;
 	}
 	if (rd890_info->gpp2_configuration == 0) {
 		platform_config.Gpp2Config = GFX_CONFIG_AAAA;
 	} else if (rd890_info->gpp2_configuration == 1) {
 		platform_config.Gpp2Config = GFX_CONFIG_AABB;
 	}
 	platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
 	if (platform_config.Gpp1Config != 0) {
 		pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
 	}
 	if (platform_config.Gpp2Config != 0) {
 		pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
 	}
 	if (platform_config.Gpp3aConfig != 0) {
 		pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
 	}
 	pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
 	for (i = 0; i <= MAX_CORE_ID; i++) {
 		NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
 		NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
 	}
 	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
 		NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
 	}
 	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
 		if ((platform_config.PortEnableMap & (1 << i)) != 0) {
 			pPcieConfig->PortConfiguration[i].PortPresent = ON;
 			if ((platform_config.PortGen1Map & (1 << i)) != 0) {
 				pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
 			}
 			if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
 				u16 j;
 				pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */
 				/* Set Hotplug descriptor info */
 				for (j = 0; j < 8; j++) {
 					u32 PortDescriptor;
 					PortDescriptor = platform_config.PortHotplugDescriptors[j];
 					if ((PortDescriptor & 0xF) == j) {
 						pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap  = (PortDescriptor >> 4)  & 3;
 						pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6)  & 1;
 						break;
 					}
 				}
 			}
 		}
 	}
 }
 #endif // __PRE_RAM__
 /**
 * @brief Entry point of Northbridge CIMx callout/CallBack
 *
 * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
 *
 * @param[in] u32 func               Northbridge CIMx CallBackId
 * @param[in] u32 data               Northbridge Input Data.
 * @param[in] AMD_NB_CONFIG *config  Northbridge configuration structure pointer.
 *
 */
 static u32 rd890_callout_entry(u32 func, u32 data, void *config)
 {
 	u32 ret = 0;
 #ifndef __PRE_RAM__
 	device_t nb_dev = (device_t)data;
 #endif
 	AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
 	switch (func) {
 		case PHCB_AmdPortTrainingCompleted:
 			break;
 		case PHCB_AmdPortResetDeassert:
 #ifndef __PRE_RAM__
 			set_pcie_dereset(config);
 #endif
 			break;
 		case PHCB_AmdPortResetAssert:
 #ifndef __PRE_RAM__
 			set_pcie_reset(config);
 #endif
 			break;
 		case PHCB_AmdPortResetSupported:
 			break;
 		case PHCB_AmdGeneratePciReset:
 			break;
 		case PHCB_AmdGetExclusionTable:
 			break;
 		case PHCB_AmdAllocateBuffer:
 			break;
 		case PHCB_AmdUpdateApicInterruptMapping:
 			break;
 		case PHCB_AmdFreeBuffer:
 			break;
 		case PHCB_AmdLocateBuffer:
 			break;
 		case PHCB_AmdReportEvent:
 			break;
 		case PHCB_AmdPcieAsmpInfo:
 			break;
 		case CB_AmdSetNbPorConfig:
 			break;
 		case CB_AmdSetHtConfig:
 			/*TODO: different HT path and deempasis for each NB */
 			nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
 			break;
 		case CB_AmdSetPcieEarlyConfig:
 #ifndef __PRE_RAM__
 			nb_platform_config(nb_dev, nbConfigPtr);
 #endif
 			break;
 		case CB_AmdSetEarlyPostConfig:
 			break;
 		case CB_AmdSetMidPostConfig:
 			nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR;
 #ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
 			/* SBIOS must alloc 16K memory for IOMMU MMIO */
 			UINT32  MmcfgBarAddress; //using default IOmmuBaseAddress
 			LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
 					AccessWidth32,
 					&MmcfgBarAddress,
 					nbConfigPtr);
 			MmcfgBarAddress &= ~0xf;
 			if (MmcfgBarAddress != 0) {
 				nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
 			}
 			nbConfigPtr->IommuBaseAddress = 0; //disable iommu
 #endif
 			break;
 		case CB_AmdSetLatePostConfig:
 			break;
 		case CB_AmdSetRecoveryConfig:
 			break;
 	}
 	return ret;
 }
 /**
 * @brief North Bridge CIMx configuration
 *
 * should be called before exeucte CIMx function.
 * this function will be called in romstage and ramstage.
 */
 void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
 {
 	u16 i = 0;
 	PCI_ADDR PciAddress;
 	u32 val, sbNode, sbLink;
 	if (!pConfig) {
 		return;
 	}
 	memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
 	for (i = 0; i < MAX_NB_COUNT; i++) {
 		pConfig->Northbridges[i].pNbConfig	= &nbConfig[i];
 		pConfig->Northbridges[i].pHtConfig	= &htConfig[i];
 		pConfig->Northbridges[i].pPcieConfig	= &pcieConfig[i];
 		pConfig->Northbridges[i].ConfigPtr	= &pConfig;
 	}
 	/* Initialize all NB structures */
 	AmdInitializer(pConfig);
 	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
 	//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
 	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
 	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
 	/*
 	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
 	 * Always 0:0:0 on single NB platform.
 	 */
 	pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
 	/* Set HT path to NB by SbNode and SbLink */
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
 	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
 	sbNode = (val >> 8) & 0x07;
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
 	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
 	sbLink = (val >> 8) & 0x07; //assum ganged
 	pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
 	pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
 	//TODO: other NBs
 #ifndef __PRE_RAM__
 	/* If temporrary MMIO enable set up CPU MMIO */
 	for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
 		UINT32  MmioBase;
 		UINT32  LinkId;
 		UINT32  SubLinkId;
 		MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
 		if (MmioBase != 0) {
 			LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
 			SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
 			/* Set Limit */
 			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
 					AccessWidth32,
 					0x0,
 					((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
 					&(pConfig->Northbridges[i]));
 			/* Set Base */
 			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
 					AccessWidth32,
 					0x0,
 					(MmioBase << 12) | 0x3,
 					&(pConfig->Northbridges[i]));
 		}
 	}
 #endif
 }
--- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h
+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
@ -0,0 +1,174 @@
 /*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 #ifndef  _RD890_CFG_H_
 #define _RD890_CFG_H_
 #include "NbPlatform.h"
 /* platform dependent configuration default value */
 /**
 * Path from CPU to NB
 * [0..7]   - Node  (0..8)
 * [8..11]  - Link  (0..3)
 * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
 */
 #ifndef DEFAULT_HT_PATH
 #if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
 #define DEFAULT_HT_PATH		{0x0, 0x3}
 #endif
 #if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
 #define DEFAULT_HT_PATH		{0x0, 0x1}
 #endif
 #endif
 /**
 * Bitmap of enabled ports on NB #0/1/2/3
 * Bit[0] - Reserved
 * Bit[1] - Reserved
 * Bit[2] - Enable PCIe port 2
 * Bit[3] - Enable PCIe port 3
 * Bit[4] - Enable PCIe port 4
 * Bit[5] - Enable PCIe port 5
 * Bit[6] - Enable PCIe port 2
 * Bit[7] - Enable PCIe port 7
 * Bit[8] - Reserved
 * Bit[9] - Enable PCIe port 9
 * Bit[10]- Enable PCIe port 10
 * Bit[11]- Enable PCIe port 11
 * Bit[12]- Enable PCIe port 12
 * Bit[13]- Enable PCIe port 13
 * Example:
 *  port_enable = 0x14
 *  Port 2 and 4 enabled for training/initialization
 */
 #ifndef DEFAULT_PORT_ENABLE_MAP
 #define DEFAULT_PORT_ENABLE_MAP		0x0014
 #endif
 /**
 * Bitmap of ports that have slot or onboard device connected.
 * Example force PCIe Gen1 supporton port 2 and 4  (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
 * #define DEFAULT_PORT_FORCE_GEN1        0x604
 */
 #ifndef DEFAULT_PORT_FORCE_GEN1
 #define DEFAULT_PORT_FORCE_GEN1		0x0
 #endif
 /**
 * Bitmap of ports that have server hotplug support
 */
 #ifndef DEFAULT_HOTPLUG_SUPPORT
 #define DEFAULT_HOTPLUG_SUPPORT		0x0
 #endif
 #ifndef DEFAULT_HOTPLUG_DESCRIPTOR
 #define DEFAULT_HOTPLUG_DESCRIPTOR		{0, 0, 0, 0, 0, 0, 0, 0}
 #endif
 #ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
 #define DEFAULT_TEMPMMIO_BASE_ADDRESS		0xD0000000
 #endif
 /**
 * Default GPP1 core configuraton on NB #0/1/2/3.
 *  2  x8 slot, GFX_CONFIG_AABB
 *  1 x16 slot, GFX_CONFIG_AAAA
 */
 #ifndef DEFAULT_GPP1_CONFIG
 #define DEFAULT_GPP1_CONFIG		GFX_CONFIG_AABB
 #endif
 /**
 * Default GPP2 core configuraton on NB #0/1/2/3.
 *  2  x8 slot, GFX_CONFIG_AABB
 *  1 x16 slot, GFX_CONFIG_AAAA
 */
 #ifndef DEFAULT_GPP2_CONFIG
 #define DEFAULT_GPP2_CONFIG		GFX_CONFIG_AABB
 #endif
 /**
 * Default GPP3a core configuraton on NB #0/1/2/3.
 * 4:2:0:0:0:0   - GPP_CONFIG_GPP420000, 0x1
 * 4:1:1:0:0:0   - GPP_CONFIG_GPP411000, 0x2
 * 2:2:2:0:0:0   - GPP_CONFIG_GPP222000, 0x3
 * 2:2:1:1:0:0   - GPP_CONFIG_GPP221100, 0x4
 * 2:1:1:1:1:0   - GPP_CONFIG_GPP211110, 0x5
 * 1:1:1:1:1:1   - GPP_CONFIG_GPP111111, 0x6
 */
 #ifndef DEFAULT_GPP3A_CONFIG
 #define DEFAULT_GPP3A_CONFIG		GPP_CONFIG_GPP111111
 #endif
 /**
 * Default HT Transmitter de-emphasis setting
 */
 #ifndef DEFAULT_HT_DEEMPASIES
 #define DEFAULT_HT_DEEMPASIES		0x3
 #endif
 /**
 * Default APIC nterrupt base for IOAPIC
 */
 #ifndef DEFAULT_APIC_INTERRUPT_BASE
 #define DEFAULT_APIC_INTERRUPT_BASE	24
 #endif
 #define DEFAULT_PLATFORM_CONFIG(name) \
 	NB_PLATFORM_CONFIG name = { \
 		DEFAULT_PORT_ENABLE_MAP, \
 		DEFAULT_PORT_FORCE_GEN1, \
 		DEFAULT_HOTPLUG_SUPPORT, \
 		DEFAULT_HOTPLUG_DESCRIPTOR, \
 		DEFAULT_TEMPMMIO_BASE_ADDRESS, \
 		DEFAULT_GPP1_CONFIG, \
 		DEFAULT_GPP2_CONFIG, \
 		DEFAULT_GPP3A_CONFIG, \
 		DEFAULT_HT_DEEMPASIES, \
 		/*DEFAULT_HT_PATH,*/ \
 		DEFAULT_APIC_INTERRUPT_BASE, \
 	}
 /**
 * Platform configuration
 */
 typedef struct {
 	UINT16  PortEnableMap;            ///< Bitmap of enabled ports
 	UINT16  PortGen1Map;              ///< Bitmap of ports to disable Gen2
 	UINT16  PortHotplugMap;           ///< Bitmap of ports support hotplug
 	UINT8   PortHotplugDescriptors[8];///< Ports Hotplug descriptors
 	UINT32  TemporaryMmio;            ///< Temporary MMIO
 	UINT32  Gpp1Config;               ///< Default PCIe GFX core configuration
 	UINT32  Gpp2Config;               ///< Default PCIe GPP2 core configuration
 	UINT32  Gpp3aConfig;              ///< Default PCIe GPP3a core configuration
 	UINT8   NbTransmitterDeemphasis;  ///< HT transmitter de-emphasis level
 	//	HT_PATH NbHtPath;                 ///< HT path to NB
 	UINT8   GlobalApicInterruptBase;  ///< Global APIC interrupt base that is used in MADT table for IO APIC.
 } NB_PLATFORM_CONFIG;
 /**
 * Bridge CIMx configuration
 */
 void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
 #endif //_RD890_CFG_H_
--- a/src/mainboard/supermicro/h8qgi/reset.c
+++ b/src/mainboard/supermicro/h8qgi/reset.c
@ -0,0 +1,66 @@
 /*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 #include <reset.h>
 #include <arch/io.h>		/*inb, outb*/
 #include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)
 #if CONFIG_MAX_PHYSICAL_CPUS > 32
 #define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 #else
 #define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
 #endif
 static inline void set_bios_reset(void)
 {
 	u32 nodes;
 	u32 htic;
 	device_t dev;
 	int i;
 	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
 	for(i = 0; i < nodes; i++) {
 		dev = NODE_PCI(i, 0);
 		htic = pci_read_config32(dev, HT_INIT_CONTROL);
 		htic &= ~HTIC_BIOSR_Detect;
 		pci_write_config32(dev, HT_INIT_CONTROL, htic);
 	}
 }
 void hard_reset(void)
 {
 	set_bios_reset();
 	/* Try rebooting through port 0xcf9 */
 	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
 	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
 	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
 }
 //SbReset();
 void soft_reset(void)
 {
 	set_bios_reset();
 	/* link reset */
 	outb(0x06, 0x0cf9);
 }
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@ -1,7 +1,7 @@
 /*
 * This file is part of the coreboot project.
 *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@ -29,9 +29,10 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "agesawrapper.h"
 #include "northbridge/amd/agesa/family10/reset_test.h"
-#include "southbridge/amd/sr5650/sr5650.h"
+#include <nb_cimx.h>
-#include "southbridge/amd/sb700/sb700.h"
+#include <sb_cimx.h>
 #include "superio/nuvoton/wpcm450/wpcm450.h"
 #include "superio/winbond/w83627dhg/w83627dhg.h"
 extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
@ -39,24 +40,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 	agesawrapper_amdinitmmio();
 	if (!cpu_init_detectedx && boot_cpu()) {
 	post_code(0x30);
-		/* SR56x0 pcie bridges block pci_locate_device() before pcie training.
+	agesawrapper_amdinitmmio();
 		 * disable all pcie bridges on SR56x0 to work around it
 		 */
 		sr5650_disable_pcie_bridge();
 	post_code(0x31);
 		sb7xx_51xx_lpc_port80();
 		post_code(0x32);
 	}
 	/* Halt if there was a built in self test failure */
 	post_code(0x33);
 	report_bist_failure(bist);
 	enable_sr5650_dev8();
 	sb7xx_51xx_lpc_init();
 	sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
 	wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
 	sb7xx_51xx_disable_wideio(0);
@ -78,7 +69,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
 	}
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x38);
 		/*
 		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
 		 * Disable all Pcie Bridges to work around It.
 		 */
 		sr56x0_rd890_disable_pcie_bridge();
 		post_code(0x39);
 		nb_Poweron_Init();
 		post_code(0x3A);
 		sb_Poweron_Init();
 	}
 	post_code(0x3B);
 	val = agesawrapper_amdinitearly();
 	if(val) {
 		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
@ -86,12 +89,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
 	}
-	sr5650_early_setup();
+	post_code(0x3C);
-	post_code(0x39);
+	nb_Ht_Init();
-
+	post_code(0x3D);
-	sb7xx_51xx_early_setup();
+	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
 	sr5650_htinit();
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
 		print_info("...WARM RESET...\n\n\n");
 		distinguish_cpu_resets(0);
@ -103,8 +104,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	val = agesawrapper_amdinitpost();
 	if (val) {
 		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
-	}
+	} else {
 		printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
 	}
 	post_code(0x41);
 	val = agesawrapper_amdinitenv();
@ -114,8 +116,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
 	post_code(0x42);
 	sr5650_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 	post_code(0x50);
 	print_debug("Disabling cache as ram ");
--- a/src/mainboard/supermicro/h8qgi/sb700_cfg.c
+++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c
@ -0,0 +1,142 @@
 /*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 #include <string.h>
 #include <console/console.h>    /* printk */
 #include "Platform.h"
 #include "sb700_cfg.h"
 /**
 * @brief South Bridge CIMx configuration
 *
 * should be called before exeucte CIMx function.
 * this function will be called in romstage and ramstage.
 */
 void sb700_cimx_config(AMDSBCFG *sb_config)
 {
 	if (!sb_config) {
 		printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n");
 		return;
 	}
 	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n");
 	memset(sb_config, 0, sizeof(AMDSBCFG));
 	/* SB_POWERON_INIT */
 	sb_config->StdHeader.Func = SB_POWERON_INIT;
 	/* header */
 	sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS;
 	/* static Build Parameters */
 	sb_config->BuildParameters.BiosSize = BIOS_SIZE;
 	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
 	sb_config->BuildParameters.EcKbd = 0;
 	sb_config->BuildParameters.EcChannel0 = 0;
 	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
 	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
 	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
 	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
 	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
 	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
 	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
 	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
 	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
 	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
 	sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT;
 	sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS;
 	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
 	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
 	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
 	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
 	sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID;
 	sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID;
 	sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID;
 	sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID;
 	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
 	sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID;
 	sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID;
 	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
 	sb_config->BuildParameters.IdeSsid = IDE_SSID;
 	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
 	sb_config->BuildParameters.LpcSsid = LPC_SSID;
 	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
 	/* General */
 	sb_config->Spi33Mhz = 1;
 	sb_config->SpreadSpectrum = 0;
 	sb_config->PciClk5 = 0;
 	sb_config->PciClks = 0x1F;
 	sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
 	sb_config->TimerClockSource = 2;  // Auto
 	sb_config->S3Resume = 0;
 	sb_config->RebootRequired = 0;
 	/* HPET */
 	sb_config->HpetTimer = HPET_TIMER;
 	/* USB */
 	sb_config->UsbIntClock = 0;     // Use external clock
 	sb_config->Usb1Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 18 Func0
 	sb_config->Usb1Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 18 Func1
 	sb_config->Usb1Ehci  = 1; //0:disable  1:enable Bus 0 Dev 18 Func2
 	sb_config->Usb2Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 19 Func0
 	sb_config->Usb2Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 19 Func1
 	sb_config->Usb2Ehci  = 1; //0:disable  1:enable Bus 0 Dev 19 Func2
 	sb_config->Usb3Ohci  = 1; //0:disable  1:enable Bus 0 Dev 20 Func5
 	sb_config->UsbOhciLegacyEmulation = 1; //0:Enable  1:Disable
 	sb_config->AcpiS1Supported = 1;
 	/* SATA */
 	sb_config->SataController = 1;
 	sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
 	sb_config->SataSmbus = 0;
 	sb_config->SataAggrLinkPmCap = 1;
 	sb_config->SataPortMultCap = 1;
 	sb_config->SataClkAutoOff = 1;
 	sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
 	//TODO: set to secondary not take effect.
 	sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
 	sb_config->SataEspPort = 0;
 	sb_config->SataClkAutoOffAhciMode = 1;
 	sb_config->SataHpcpButNonESP = 0;
 	sb_config->SataHideUnusedPort = 0;
 	/* Azalia HDA */
 	sb_config->AzaliaController = AZALIA_CONTROLLER;
 	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
 	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN;
 	sb_config->pAzaliaOemCodecTablePtr = NULL;
 #ifndef __PRE_RAM__
 	/* ramstage cimx config here */
 	if (!sb_config->StdHeader.pCallBack) {
 		sb_config->StdHeader.pCallBack = sb700_callout_entry;
 	}
 	//sb_config->
 #endif //!__PRE_RAM__
 	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n");
 }
--- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h
+++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
@ -0,0 +1,237 @@
 /*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 #ifndef _SB700_CFG_H_
 #define _SB700_CFG_H_
 #include <stdint.h>
 /**
 * @def BIOS_SIZE_1M
 * @def BIOS_SIZE_2M
 * @def BIOS_SIZE_4M
 * @def BIOS_SIZE_8M
 */
 #define BIOS_SIZE_1M                    0
 #define BIOS_SIZE_2M                    1
 #define BIOS_SIZE_4M                    3
 #define BIOS_SIZE_8M                    7
 /* In SB700, default ROM size is 1M Bytes, if your platform ROM
 * bigger than 1M you have to set the ROM size outside CIMx module and
 * before AGESA module get call.
 */
 #ifndef BIOS_SIZE
 #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
 #define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
 #define BIOS_SIZE BIOS_SIZE_2M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
 #define BIOS_SIZE BIOS_SIZE_4M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
 #define BIOS_SIZE BIOS_SIZE_8M
 #endif
 #endif
 /**
 * @def SPREAD_SPECTRUM
 * @brief
 *  0 - Disable Spread Spectrum function
 *  1 - Enable  Spread Spectrum function
 */
 #define SPREAD_SPECTRUM                 0
 /**
 * @def SB_HPET_TIMER
 * @breif
 *  0 - Disable hpet
 *  1 - Enable  hpet
 */
 #define HPET_TIMER                      1
 /**
 * @def USB_CONFIG
 * @brief bit[0-6] used to control USB
 *   0 - Disable
 *   1 - Enable
 *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
 *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
 *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
 *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
 *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
 *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
 *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
 */
 #define USB_CINFIG              0x7F
 /**
 * @def PCI_CLOCK_CTRL
 * @breif bit[0-4] used for PCI Slots Clock Control,
 *   0 - disable
 *   1 - enable
 *  PCI SLOT 0 define at BIT0
 *  PCI SLOT 1 define at BIT1
 *  PCI SLOT 2 define at BIT2
 *  PCI SLOT 3 define at BIT3
 *  PCI SLOT 4 define at BIT4
 */
 #define PCI_CLOCK_CTRL                  0x1F
 /**
 * @def SATA_CONTROLLER
 * @breif INCHIP Sata Controller
 */
 #ifndef SATA_CONTROLLER
 #define SATA_CONTROLLER               1
 #endif
 /**
 * @def SATA_MODE
 * @breif INCHIP Sata Controller Mode
 *   NOTE: DO NOT ALLOW SATA & IDE use same mode
 */
 #ifndef SATA_MODE
 #define SATA_MODE                     NATIVE_IDE_MODE
 #endif
 /**
 * @breif INCHIP Sata IDE Controller Mode
 */
 #define IDE_LEGACY_MODE                 0
 #define IDE_NATIVE_MODE                 1
 /**
 * @def SATA_IDE_MODE
 * @breif INCHIP Sata IDE Controller Mode
 *   NOTE: DO NOT ALLOW SATA & IDE use same mode
 */
 #ifndef SATA_IDE_MODE
 #define SATA_IDE_MODE                 IDE_LEGACY_MODE
 #endif
 /**
 * @def EXTERNAL_CLOCK
 * @brief 00/10: Reference clock from crystal oscillator via
 *  PAD_XTALI and PAD_XTALO
 *
 * @def INTERNAL_CLOCK
 * @brief 01/11: Reference clock from internal clock through
 *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
 */
 #define EXTERNAL_CLOCK          0x00
 #define INTERNAL_CLOCK          0x01
 #define SATA_CLOCK_SOURCE       EXTERNAL_CLOCK
 /**
 * @def SATA_PORT_MULT_CAP_RESERVED
 * @brief 1 ON, 0 0FF
 */
 #define SATA_PORT_MULT_CAP_RESERVED     1
 /**
 * @def   AZALIA_AUTO
 * @brief Detect Azalia controller automatically.
 *
 * @def   AZALIA_DISABLE
 * @brief Disable Azalia controller.
 * @def   AZALIA_ENABLE
 * @brief Enable Azalia controller.
 */
 #define AZALIA_AUTO                     0
 #define AZALIA_DISABLE                  1
 #define AZALIA_ENABLE                   2
 /**
 * @breif INCHIP HDA controller
 */
 #ifndef AZALIA_CONTROLLER
 #define AZALIA_CONTROLLER             AZALIA_AUTO
 #endif
 /**
 * @def AZALIA_PIN_CONFIG
 * @brief
 *  0 - disable
 *  1 - enable
 */
 #ifndef AZALIA_PIN_CONFIG
 #define AZALIA_PIN_CONFIG             1
 #endif
 /**
 * @def AZALIA_SDIN_PIN
 * @brief
 *  SDIN0 is define at BIT0 & BIT1
 *   00 - GPIO PIN
 *   01 - Reserved
 *   10 - As a Azalia SDIN pin
 *  SDIN1 is define at BIT2 & BIT3
 *  SDIN2 is define at BIT4 & BIT5
 *  SDIN3 is define at BIT6 & BIT7
 */
 #ifndef AZALIA_SDIN_PIN
 //#define AZALIA_SDIN_PIN             0xAA
 #define AZALIA_SDIN_PIN               0x2A
 #endif
 /**
 * @def GPP_CONTROLLER
 */
 #ifndef GPP_CONTROLLER
 #define GPP_CONTROLLER                1
 #endif
 /**
 * @def GPP_CFGMODE
 * @brief GPP Link Configuration
 * four possible configuration:
 *  GPP_CFGMODE_X4000
 *  GPP_CFGMODE_X2200
 *  GPP_CFGMODE_X2110
 *  GPP_CFGMODE_X1111
 */
 #ifndef GPP_CFGMODE
 #define GPP_CFGMODE                   GPP_CFGMODE_X1111
 #endif
 /**
 * @brief South Bridge CIMx configuration
 *
 */
 void sb700_cimx_config(AMDSBCFG *sb_cfg);
 /**
 * @brief Entry point of Southbridge CIMx callout
 *
 * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
 *
 * @param[in] func    Southbridge CIMx Function ID.
 * @param[in] data    Southbridge Input Data.
 * @param[in] sb_cfg  Southbridge configuration structure pointer.
 *
 */
 u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg);
 #endif //_SB700_CFG_H_