mt8173: add SPI NOR support

BRANCH=none
BUG=none
TEST=boot oak to kernel on rev1

Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae
Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18
Original-Signed-off-by: mtk05962 <bayi.cheng@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292693
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/oak/Kconfig

@@ -20,14 +20,16 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_MEDIATEK_MT8173
 	select BOARD_ID_AUTO
 	select BOARD_ROMSIZE_KB_4096
+	select COMMON_CBFS_SPI_WRAPPER
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_SPI
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select MAINBOARD_DO_NATIVE_VGA_INIT
 	select MAINBOARD_HAS_CHROMEOS
+	select SPI_FLASH
 
 config CHROMEOS
-	select CHROMEOS_VBNV_EC
+	select CHROMEOS_VBNV_FLASH
 	select EC_SOFTWARE_SYNC
 	select VIRTUAL_DEV_SWITCH
 
@@ -55,6 +57,10 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x20
 
+config BOOT_MEDIA_SPI_BUS
+	int
+	default 9
+
 config EC_GOOGLE_CHROMEEC_BOARDNAME
 	string
 	default "oak"

src/mainboard/google/oak/bootblock.c

@@ -33,6 +33,34 @@ static void i2c_set_gpio_pinmux(void)
 	gpio_set_mode(PAD_SCL4, PAD_SCL4_FUNC_SCL4);
 }
 
+static void nor_set_gpio_pinmux(void)
+{
+	/* Set driving strength of EINT4~EINT9 to 8mA
+	 * 0: 2mA
+	 * 1: 4mA
+	 * 2: 8mA
+	 * 3: 16mA
+	 */
+	/* EINT4: 0x10005B20[14:13] */
+	clrsetbits_le16(&mt8173_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
+	/* EINT5~EINT9: 0x10005B30[2:1] */
+	clrsetbits_le16(&mt8173_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
+
+	gpio_set_pull(PAD_EINT4, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT5, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT6, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT7, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT8, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT9, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+
+	gpio_set_mode(PAD_EINT4, PAD_EINT4_FUNC_SFWP_B);
+	gpio_set_mode(PAD_EINT5, PAD_EINT5_FUNC_SFOUT);
+	gpio_set_mode(PAD_EINT6, PAD_EINT6_FUNC_SFCS0);
+	gpio_set_mode(PAD_EINT7, PAD_EINT7_FUNC_SFHOLD);
+	gpio_set_mode(PAD_EINT8, PAD_EINT8_FUNC_SFIN);
+	gpio_set_mode(PAD_EINT9, PAD_EINT9_FUNC_SFCK);
+}
+
 void bootblock_mainboard_early_init(void)
 {
 	/* Clear UART0 power down signal */
@@ -47,6 +75,9 @@ void bootblock_mainboard_init(void)
 	/* set i2c related gpio */
 	i2c_set_gpio_pinmux();
 
+	/* set nor related GPIO */
+	nor_set_gpio_pinmux();
+
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
 
 	setup_chromeos_gpios();

src/soc/mediatek/mt8173/Makefile.inc

@@ -16,7 +16,7 @@
 ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y)
 
 bootblock-y += bootblock.c
-bootblock-y += cbfs.c
+bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
 bootblock-y += pll.c
 bootblock-y += spi.c
 bootblock-y += timer.c
@@ -38,11 +38,11 @@ verstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 verstage-y += timer.c
 verstage-y += wdt.c
-verstage-y += cbfs.c
+verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
 
 ################################################################################
 
-romstage-y += cbfs.c
+romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
 romstage-y += timer.c
 
 romstage-$(CONFIG_DRIVERS_UART) += uart.c
@@ -57,7 +57,7 @@ romstage-y += rtc.c
 
 ramstage-y += cbmem.c
 ramstage-y += spi.c
-ramstage-y += cbfs.c
+ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
 ramstage-y += soc.c mtcmos.c
 ramstage-y += timer.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c

src/soc/mediatek/mt8173/cbfs.c

@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 MediaTek Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <boot_device.h>
-
-const struct region_device *boot_device_ro(void)
-{
-	return NULL;
-}

src/soc/mediatek/mt8173/flash_controller.c

@@ -0,0 +1,184 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* NOR Flash is clocked with 26MHz, from CLK26M -> TOP_SPINFI_IFR */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <console/console.h>
+#include <spi_flash.h>
+#include <spi-generic.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <timer.h>
+#include <soc/flash_controller.h>
+
+#define get_nth_byte(d, n)	((d >> (8 * n)) & 0xff)
+
+static int polling_cmd(u32 val)
+{
+	struct stopwatch sw;
+
+	stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US);
+
+	while ((read32(&mt8173_nor->cmd) & val) != 0) {
+		if (stopwatch_expired(&sw))
+			return -1;
+	}
+
+	return 0;
+}
+
+static int mt8173_nor_execute_cmd(u8 cmdval)
+{
+	u8 val = cmdval & ~(SFLASH_AUTOINC);
+
+	write8(&mt8173_nor->cmd, cmdval);
+	return polling_cmd(val);
+}
+
+static int sflashhw_read_flash_status(u8 *value)
+{
+	if (mt8173_nor_execute_cmd(SFLASH_READSTATUS))
+		return -1;
+
+	*value = read8(&mt8173_nor->rdsr);
+	return 0;
+}
+
+static int wait_for_write_done(void)
+{
+	struct stopwatch sw;
+	u8 reg;
+
+	stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US);
+
+	while (sflashhw_read_flash_status(&reg) == 0) {
+		if (!(reg & SFLASH_WRITE_IN_PROGRESS))
+			return 0;
+		if (stopwatch_expired(&sw))
+			return -1;
+	}
+
+	return -1;
+}
+
+/* set serial flash program address */
+static void set_sfpaddr(u32 addr)
+{
+	write8(&mt8173_nor->radr[2], get_nth_byte(addr, 2));
+	write8(&mt8173_nor->radr[1], get_nth_byte(addr, 1));
+	write8(&mt8173_nor->radr[0], get_nth_byte(addr, 0));
+}
+
+static int sector_erase(int offset)
+{
+	if (wait_for_write_done())
+		return -1;
+
+	write8(&mt8173_nor->prgdata[5], SFLASH_OP_WREN);
+	write8(&mt8173_nor->cnt, 8);
+	mt8173_nor_execute_cmd(SFLASH_PRG_CMD);
+
+	write8(&mt8173_nor->prgdata[5], SECTOR_ERASE_CMD);
+	write8(&mt8173_nor->prgdata[4], get_nth_byte(offset, 2));
+	write8(&mt8173_nor->prgdata[3], get_nth_byte(offset, 1));
+	write8(&mt8173_nor->prgdata[2], get_nth_byte(offset, 0));
+	write8(&mt8173_nor->cnt, 32);
+	mt8173_nor_execute_cmd(SFLASH_PRG_CMD);
+
+	if (wait_for_write_done())
+		return -1;
+
+	return 0;
+}
+
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+	return min(65535, buf_len);
+}
+
+static int nor_read(struct spi_flash *flash, u32 addr, size_t len, void *buf)
+{
+	u8 *buffer = (u8 *)buf;
+
+	set_sfpaddr(addr);
+	while (len) {
+		if (mt8173_nor_execute_cmd(SFLASH_RD_TRIGGER | SFLASH_AUTOINC))
+			return -1;
+
+		*buffer++ = read8(&mt8173_nor->rdata);
+		len--;
+	}
+	return 0;
+}
+
+static int nor_write(struct spi_flash *flash, u32 addr, size_t len,
+		       const void *buf)
+{
+	const u8 *buffer = (const u8 *)buf;
+
+	set_sfpaddr(addr);
+	while (len) {
+		write8(&mt8173_nor->wdata, *buffer);
+		if (mt8173_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC))
+			return -1;
+
+		if (wait_for_write_done())
+			return -1;
+		buffer++;
+		len--;
+	}
+	return 0;
+}
+
+static int nor_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+	int sector_start = offset;
+	int sector_num = (u32)len / flash->sector_size;
+
+	while (sector_num) {
+		if (!sector_erase(sector_start)) {
+			sector_start += flash->sector_size;
+			sector_num--;
+		} else {
+			printk(BIOS_WARNING, "Erase failed at 0x%x!\n",
+			       sector_start);
+			return -1;
+		}
+	}
+	return 0;
+}
+
+struct spi_flash *mt8173_nor_flash_probe(struct spi_slave *spi)
+{
+	static struct spi_flash flash = {0};
+
+	if (flash.spi)
+		return &flash;
+
+	write32(&mt8173_nor->wrprot, SFLASH_COMMAND_ENABLE);
+	flash.spi = spi;
+	flash.name = "mt8173 flash controller";
+	flash.write = nor_write;
+	flash.erase = nor_erase;
+	flash.read = nor_read;
+	flash.status = 0;
+	flash.sector_size = 0x1000;
+	flash.erase_cmd = SECTOR_ERASE_CMD;
+	flash.size = CONFIG_ROM_SIZE;
+	return &flash;
+}

src/soc/mediatek/mt8173/include/soc/flash_controller.h

@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__
+#define __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__
+
+#include <cbfs.h>
+#include <spi-generic.h>
+#include <stdint.h>
+#include <soc/addressmap.h>
+
+enum {
+	SFLASH_POLLINGREG_US	  = 500000,
+	SFLASH_WRBUF_SIZE	  = 128,
+	SFLASHNAME_LENGTH	  = 16,
+	SFLASH_WRITE_IN_PROGRESS  = 1,
+	SFLASH_COMMAND_ENABLE	  = 0x30,
+
+	/* NOR flash controller commands */
+	SFLASH_RD_TRIGGER	  = 1 << 0,
+	SFLASH_READSTATUS	  = 1 << 1,
+	SFLASH_PRG_CMD		  = 1 << 2,
+	SFLASH_WR_TRIGGER	  = 1 << 4,
+	SFLASH_WRITESTATUS	  = 1 << 5,
+	SFLASH_AUTOINC		  = 1 << 7,
+	/* NOR flash commands */
+	SFLASH_OP_WREN		  = 0x6,
+	SECTOR_ERASE_CMD	  = 0x20,
+	SFLASH_UNPROTECTED	  = 0x0
+};
+
+/* register Offset */
+struct mt8173_nor_regs {
+	u32 cmd;
+	u32 cnt;
+	u32 rdsr;
+	u32 rdata;
+	u32 radr[3];
+	u32 wdata;
+	u32 prgdata[6];
+	u32 shreg[10];
+	u32 cfg[2];
+	u32 shreg10;
+	u32 status[5];
+	u32 timing;
+	u32 flash_cfg;
+	u32 reserved2[3];
+	u32 sf_time;
+	u32 reserved3;
+	u32 diff_addr;
+	u32 del_sel[2];
+	u32 intrstus;
+	u32 intren;
+	u32 pp_ctl;
+	u32 cfg3;
+	u32 chksum_ctl;
+	u32 chksum;
+	u32 aaicmd;
+	u32 wrprot;
+	u32 radr3;
+	u32 read_dual;
+	u32 delsel[3];
+};
+check_member(mt8173_nor_regs, delsel[2], 0xD8);
+static struct mt8173_nor_regs * const mt8173_nor = (void *)SFLASH_REG_BASE;
+
+struct spi_flash *mt8173_nor_flash_probe(struct spi_slave *spi);
+#endif /* __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ */

src/soc/mediatek/mt8173/spi.c

@@ -23,6 +23,7 @@
 #include <string.h>
 #include <timer.h>
 #include <soc/addressmap.h>
+#include <soc/flash_controller.h>
 #include <soc/gpio.h>
 #include <soc/pinmux.h>
 #include <soc/pll.h>
@@ -161,6 +162,7 @@ static void mtk_spi_dump_data(const char *name, const uint8_t *data,
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
 {
 	struct mtk_spi_bus *eslave;
+	static struct spi_slave slave;
 
 	switch (bus) {
 	case CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS:
@@ -168,6 +170,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
 		assert(read32(&eslave->regs->spi_cfg0_reg) != 0);
 		spi_sw_reset(eslave->regs);
 		return &eslave->slave;
+	case CONFIG_BOOT_MEDIA_SPI_BUS:
+		slave.bus = bus;
+		slave.cs = cs;
+		slave.force_programmer_specific = 1;
+		slave.programmer_specific_probe = &mt8173_nor_flash_probe;
+		return &slave;
 	default:
 		die ("wrong bus number.\n");
 	};