added early_setup.c
removed some messages git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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070a1e02d0
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@ -65,7 +65,6 @@ static void main(unsigned long bist)
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cs5535_early_setup();
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pll_reset();
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//msr_init();
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/* Halt if there was a built in self test failure */
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//report_bist_failure(bist);
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@ -18,7 +18,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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/* 1. Initialize GLMC registers base on SPD values,
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* Hard coded as XpressROM for now */
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print_debug("sdram_enable step 1\r\n");
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//print_debug("sdram_enable step 1\r\n");
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msr = rdmsr(0x20000018);
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msr.hi = 0x10076013;
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msr.lo = 0x00003000;
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@ -39,13 +39,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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msr = rdmsr(0x2000001a);
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msr.lo = 0x0101;
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wrmsr(0x2000001a, msr);
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print_debug("sdram_enable step 2\r\n");
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//print_debug("sdram_enable step 2\r\n");
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/* 3. release CKE mask to enable CKE */
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msr = rdmsr(0x2000001d);
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msr.lo &= ~(0x03 << 8);
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wrmsr(0x2000201d, msr);
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print_debug("sdram_enable step 3\r\n");
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//print_debug("sdram_enable step 3\r\n");
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/* 4. set and clear REF_TST 16 times, more shouldn't hurt
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* why this is before EMRS and MRS ? */
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@ -56,7 +56,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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msr.lo &= ~(0x01 << 3);
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wrmsr(0x20000018, msr);
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}
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print_debug("sdram_enable step 4\r\n");
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//print_debug("sdram_enable step 4\r\n");
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/* 5. set refresh interval */
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msr = rdmsr(0x20000018);
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@ -68,7 +68,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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msr.lo &= ~(0x03 << 6);
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msr.lo |= (0x00 << 6);
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wrmsr(0x20000018, msr);
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print_debug("sdram_enable step 5\r\n");
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//print_debug("sdram_enable step 5\r\n");
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/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
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msr = rdmsr(0x20000018);
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@ -76,7 +76,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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wrmsr(0x20000018, msr);
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msr.lo &= ~((0x01 << 28) | 0x01);
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wrmsr(0x20000018, msr);
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print_debug("sdram_enable step 6\r\n");
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//print_debug("sdram_enable step 6\r\n");
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/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
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* it is documented in LX datasheet */
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@ -86,7 +86,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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wrmsr(0x20000018, msr);
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msr.lo &= ~((0x01 << 27) | 0x01);
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wrmsr(0x20000018, msr);
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print_debug("sdram_enable step 7\r\n");
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//print_debug("sdram_enable step 7\r\n");
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/* 8. load Mode Register by set and clear PROG_DRAM */
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msr = rdmsr(0x20000018);
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@ -94,7 +94,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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wrmsr(0x20000018, msr);
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msr.lo &= ~0x01;
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wrmsr(0x20000018, msr);
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print_debug("sdram_enable step 8\r\n");
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//print_debug("sdram_enable step 8\r\n");
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/* wait 200 SDCLKs */
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for (i = 0; i < 200; i++)
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@ -0,0 +1,113 @@
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/*
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*
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* cs5535_early_setup.c: Early chipset initialization for CS5535 companion device
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*
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*
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* This file implements the initialization sequence documented in section 4.2 of
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* AMD Geode GX Processor CS5535 Companion Device GoedeROM Porting Guide.
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*
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*/
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#define CS5535_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5535 */
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#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */
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/**
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* @brief Setup PCI IDSEL for CS5535
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*
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*
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*/
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static void cs5535_setup_extmsr(void)
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{
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msr_t msr;
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/* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */
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msr.hi = msr.lo = 0x00000000;
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if (CS5535_GLINK_PORT_NUM <= 4) {
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msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8);
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} else {
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msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8);
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}
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wrmsr(0x5000201e, msr);
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}
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static void cs5535_setup_idsel(void)
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{
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/* write IDSEL to the write once register at address 0x0000 */
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outl(0x1 << (CS5535_DEV_NUM + 10), 0);
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}
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static int cs5535_setup_iobase(void)
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{
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msr_t msr;
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/* setup LBAR for SMBus controller */
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__builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
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/* setup LBAR for GPIO */
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__builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001);
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/* setup LBAR for MFGPT */
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__builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
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/* setup LBAR for ACPI */
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__builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
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/* setup LBAR for MFGPT */
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__builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
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}
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static void cs5535_setup_gpio(void)
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{
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uint32_t val;
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/* setup GPIO pins 14/15 for SDA/SCL */
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val = (1<<14 | 1<<15);
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/* Output Enable */
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outl(0x3fffc000, 0x6100 + 0x04);
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//outl(val, 0x6100 + 0x04);
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/* Output AUX1 */
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outl(0x3fffc000, 0x6100 + 0x10);
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//outl(val, 0x6100 + 0x10);
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/* Input Enable */
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//outl(0x0f5af0a5, 0x6100 + 0x20);
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outl(0x3fffc000, 0x6100 + 0x20);
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//outl(val, 0x6100 + 0x20);
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/* Input AUX1 */
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//outl(0x3ffbc004, 0x6100 + 0x34);
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outl(0x3fffc000, 0x6100 + 0x34);
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//outl(val, 0x6100 + 0x34);
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}
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static void cs5535_setup_cis_mode(void)
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{
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msr_t msr;
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/* setup CPU interface serial to mode C on both sides */
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msr = __builtin_rdmsr(0x51000010);
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msr.lo &= ~0x18;
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msr.lo |= 0x10;
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__builtin_wrmsr(0x51000010, msr.lo, msr.hi);
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__builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
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}
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static void dummy(void)
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{
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}
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static int cs5535_early_setup(void)
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{
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msr_t msr;
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cs5535_setup_extmsr();
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msr = rdmsr(0x4c000014);
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if (msr.lo & (0x3f << 26)) {
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/* PLL is already set and we are reboot from PLL reset */
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print_debug("reboot from BIOS reset\n\r");
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return;
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}
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cs5535_setup_idsel();
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cs5535_setup_iobase();
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cs5535_setup_gpio();
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cs5535_setup_cis_mode();
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cs5535_enable_smbus();
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//get_memory_speed();
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dummy();
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}
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@ -11,7 +11,7 @@ static int cs5535_enable_smbus(void)
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/* Set SCL freq and enable SMB controller */
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val = inb(SMBUS_IO_BASE + SMB_CTRL2);
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val |= ((0x7F << 1) | SMB_CTRL2_ENABLE);
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val |= ((0x20 << 1) | SMB_CTRL2_ENABLE);
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outb(val, SMBUS_IO_BASE + SMB_CTRL2);
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/* Setup SMBus host controller address to 0xEF */
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