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samus: Updates for P2 board 

- RAM ID3 moved to GPIO65 to avoid Top Block Swap strap on GPIO66
- LTE_POWER_ON connection removed

BUG=chrome-os-partner:29502
BRANCH=None
TEST=none yet, preparing for new board

Original-Change-Id: I521fe963cbed57ef5f56cfb0e89aec50bfc48b21
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203186
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 1eb65e058307a172f0af9c27d2d2d87d1b78c514)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibf16dcfd83242c487232f34a310c9f6b2cb69314
Reviewed-on: http://review.coreboot.org/8131
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie 2014-06-10 10:06:46 -07:00 committed by Marc Jones
parent dbadb1dd63
commit a416f212dc
2 changed files with 4 additions and 4 deletions
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6
src/mainboard/google/samus/gpio.h
View File

@ -90,12 +90,12 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */ PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */ PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */
PCH_GPIO_UNUSED, /* 65: UNUSED */ PCH_GPIO_INPUT, /* 65: RAM_ID3 */
PCH_GPIO_INPUT, /* 66: RAM_ID3 */ PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
PCH_GPIO_INPUT, /* 67: RAM_ID0 */ PCH_GPIO_INPUT, /* 67: RAM_ID0 */
PCH_GPIO_INPUT, /* 68: RAM_ID1 */ PCH_GPIO_INPUT, /* 68: RAM_ID1 */
PCH_GPIO_INPUT, /* 69: RAM_ID2 */ PCH_GPIO_INPUT, /* 69: RAM_ID2 */
PCH_GPIO_OUT_HIGH, /* 70: LTE_POWER_ON */ PCH_GPIO_UNUSED, /* 70: UNUSED */
PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
PCH_GPIO_UNUSED, /* 72: UNUSED */ PCH_GPIO_UNUSED, /* 72: UNUSED */
PCH_GPIO_UNUSED, /* 73: UNUSED */ PCH_GPIO_UNUSED, /* 73: UNUSED */

2
src/mainboard/google/samus/spd/spd.h
View File

@ -36,7 +36,7 @@
#define SPD_GPIO_BIT0 67 #define SPD_GPIO_BIT0 67
#define SPD_GPIO_BIT1 68 #define SPD_GPIO_BIT1 68
#define SPD_GPIO_BIT2 69 #define SPD_GPIO_BIT2 69
#define SPD_GPIO_BIT3 66 #define SPD_GPIO_BIT3 65
struct pei_data; struct pei_data;
void mainboard_fill_spd_data(struct pei_data *pei_data); void mainboard_fill_spd_data(struct pei_data *pei_data);