soc/intel/tgl/pcie_rp: correct root port map

TGL-LP only has 12 root ports, not 20. Correct the port map.

Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>

src/soc/intel/tigerlake/pcie_rp.c

@@ -8,8 +8,7 @@
 
 static const struct pcie_rp_group pch_lp_rp_groups[] = {
 	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8 },
-	{ .slot = PCH_DEV_SLOT_PCIE_2,	.count = 4 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4 },
 	{ 0 }
 };