cpu/amd/family_10h-family_15h: transition away from device_t
Replace the use of the old device_t definition inside cpu/amd/family_10h-family_15h. Change-Id: Ia1b155eeb7b67d94cf7aaa7789843a3e4ed3497a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16436 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -122,7 +122,7 @@ static void enable_fid_change(u8 fid)
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{
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u32 dword;
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u32 nodes;
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device_t dev;
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pci_devfn_t dev;
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int i;
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nodes = get_nodes();
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@ -139,7 +139,8 @@ static void enable_fid_change(u8 fid)
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}
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}
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static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) {
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static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid)
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{
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// BKDG 2.4.2.8
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// Fam10h revision E only, but E is apparently not supported yet, therefore untested
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if ((cpuid_edx(0x80000007) & CPB_MASK)
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@ -164,7 +165,8 @@ static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) {
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}
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}
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static void enableNbPState1( device_t dev ) {
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static void enableNbPState1(pci_devfn_t dev)
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{
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uint64_t cpuRev = mctGetLogicalCPUID(0xFF);
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if (cpuRev & AMD_FAM10_C3) {
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u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
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@ -184,7 +186,8 @@ static void enableNbPState1( device_t dev ) {
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}
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}
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static u8 setPStateMaxVal(device_t dev) {
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static u8 setPStateMaxVal(pci_devfn_t dev)
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{
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u8 i, maxpstate=0;
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for (i = 0; i < NM_PS_REG; i++) {
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msr_t msr = rdmsr(PS_REG_BASE + i);
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@ -204,7 +207,8 @@ static u8 setPStateMaxVal(device_t dev) {
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return maxpstate;
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}
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static void dualPlaneOnly( device_t dev ) {
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static void dualPlaneOnly(pci_devfn_t dev)
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{
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// BKDG 2.4.2.7
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uint64_t cpuRev = mctGetLogicalCPUID(0xFF);
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@ -248,7 +252,8 @@ static int vidTo100uV(u8 vid)
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return voltage;
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}
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static void setVSRamp(device_t dev) {
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static void setVSRamp(pci_devfn_t dev)
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{
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/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime]
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* If this field accepts 8 values between 10 and 500 us why
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* does page 324 say "BIOS should set this field to 001b."
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@ -263,7 +268,7 @@ static void setVSRamp(device_t dev) {
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pci_write_config32(dev, 0xd8, dword);
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}
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static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
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static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev)
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{
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u8 pviModeFlag;
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u8 highVoltageVid, lowVoltageVid, bValue;
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@ -447,7 +452,8 @@ static u32 power_up_down(int node, u8 procPkg) {
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}
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static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) {
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device_t dev = NODE_PCI(node, 3);
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pci_devfn_t dev = NODE_PCI(node, 3);
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/* Program fields in Clock Power/Control register0 (F3xD4) */
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@ -471,7 +477,9 @@ static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t pr
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}
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static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
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static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev,
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uint8_t procPkg)
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{
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/* check PVI/SVI */
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uint32_t dword = pci_read_config32(dev, 0xa0);
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@ -504,7 +512,8 @@ static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t pr
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pci_write_config32(dev, 0xa0, dword);
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}
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static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) {
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static void config_nb_syn_ptr_adj(pci_devfn_t dev, uint64_t cpuRev)
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{
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/* Note the following settings are additional from the ported
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* function setFidVidRegs()
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*/
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@ -526,7 +535,9 @@ static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) {
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pci_write_config32(dev, 0xdc, dword);
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}
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static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
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static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev,
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uint8_t procPkg)
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{
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if (is_fam15h()) {
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/* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */
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pci_write_config32(dev, 0x80, 0xe20be281);
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@ -594,7 +605,7 @@ static void prep_fid_change(void)
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{
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u32 dword;
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u32 nodes;
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device_t dev;
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pci_devfn_t dev;
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int i;
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/* This needs to be run before any Pstate changes are requested */
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@ -809,7 +820,7 @@ static u32 needs_NB_COF_VID_update(void)
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static u32 init_fidvid_core(u32 nodeid, u32 coreid)
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{
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device_t dev;
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pci_devfn_t dev;
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u32 vid_max;
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u32 fid_max = 0;
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u8 nb_cof_vid_update = needs_NB_COF_VID_update();
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@ -973,7 +984,7 @@ static void finalPstateChange(void)
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static void init_fidvid_stage2(u32 apicid, u32 nodeid)
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{
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msr_t msr;
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device_t dev;
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pci_devfn_t dev;
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u32 reg1fc;
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u32 dtemp;
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u32 nbvid;
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@ -541,7 +541,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
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static u32 is_core0_started(u32 nodeid)
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{
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u32 htic;
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device_t device;
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pci_devfn_t device;
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device = NODE_PCI(nodeid, 0);
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htic = pci_read_config32(device, HT_INIT_CONTROL);
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htic &= HTIC_ColdR_Detect;
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