soc/intel/cannonlake: Implement soc side VMX support

Implement required soc side API to enable VMX support using CPU_COMMON

BUG=b:124518711
TEST= read msr 0x3a and verify vmx is enabled (value should be 5).

Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/cannonlake/Kconfig

@@ -67,6 +67,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CACHE_MRC_SETTINGS
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select COMMON_FADT
+	select CPU_INTEL_COMMON
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select FSP_M_XIP
 	select GENERIC_GPIO_LIB

src/soc/intel/cannonlake/Makefile.inc

@@ -7,6 +7,7 @@ subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
+subdirs-y += ../../../cpu/intel/common
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/cpu.c

src/soc/intel/cannonlake/cpu.c

@@ -33,6 +33,7 @@
 #include <soc/systemagent.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/common/common.h>
 
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
 static const u8 power_limit_time_sec_to_msr[] = {
@@ -437,6 +438,9 @@ void soc_core_init(struct device *cpu)
 
 	/* Enable Turbo */
 	enable_turbo();
+
+	/* Enable Vmx */
+	set_vmx_and_lock();
 }
 
 static void per_cpu_smm_trigger(void)