Add initial support for the ASI/BCom MB-5BLMP mainboard, as used in
the IGEL Winnet III thin client. It boots a Linux kernel, but there are some problems. The login prompt is never reached, it simply hangs at some point. One possible reason is the IRQ table, which needs fixing. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
6b83e46f3b
commit
a440f7fd8c
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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##
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## Romcc output
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##
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# makerule ./failover.E
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# depends "$(MAINBOARD)/failover.c ./romcc"
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# action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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# end
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#
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# makerule ./failover.inc
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# depends "$(MAINBOARD)/failover.c ./romcc"
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# action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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# end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c ./romcc"
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action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c ./romcc"
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action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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# if USE_FALLBACK_IMAGE
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# ldscript /arch/i386/lib/failover.lds
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# mainboardinit ./failover.inc
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# end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/amd/model_gx1/cpu_setup.inc
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mainboardinit cpu/amd/model_gx1/gx_setup.inc
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mainboardinit ./auto.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/amd/gx1 # Northbridge
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/amd/cs5530 # Southbridge
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device pci 12.0 on
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chip superio/nsc/pc87351 # Super I/O
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device pnp 2e.0 on # PIC
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io 0x60 = 0x20
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io 0x62 = 0xa0
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irq 0x70 = 2
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end
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device pnp 2e.1 on # DMA
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end
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device pnp 2e.2 on # System Timer
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io 0x60 = 0x40
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irq 0x70 = 0
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end
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device pnp 2e.3 on # RTC
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io 0x60 = 0x70
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irq 0x70 = 8
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end
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device pnp 2e.4 on # Keyboard + Mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.5 on # PC Speaker
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end
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device pnp 2e.6 on # Math Coprocessor (FPU)
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io 0x60 = 0xf0
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irq 0x70 = 13
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end
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device pnp 2e.7 on # System board
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end
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device pnp 2e.8 on # Motherboard resources
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end
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device pnp 2e.9 on # PCI bus
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end
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device pnp 2e.c on # Motherboard resources
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end
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device pnp 2e.d on # Motherboard resources
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end
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device pnp 2e.e on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.f off # FDC
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end
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device pnp 2e.10 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.12 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end
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device pci 12.1 off end # SMI
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device pci 12.2 on end # IDE
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device pci 12.3 off end # Audio
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device pci 12.4 off end # Video (VGA)
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end
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# device pci 12.4 on # VGA (onboard)
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# chip drivers/pci/onboard
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# device pci 12.4 on end
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# register "rom_address" = "0xfffc0000" # 256 KB image
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# # register "rom_address" = "0xfff80000" # 512 KB image
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# # register "rom_address" = "0xfff00000" # 1 MB image
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# end
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# end
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device pci 0f.0 off end # Ethernet (Realtek RTL8139B)
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device pci 13.0 on end # USB
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end
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end
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chip cpu/amd/model_gx1 # CPU
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end
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end
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses CONFIG_ROM_PAYLOAD
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD_START
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# uses CONFIG_COMPRESS
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# uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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# uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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# uses CONFIG_CONSOLE_VGA
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# uses CONFIG_PCI_ROM_RUN
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256 * 1024
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=0
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## Delay timer options
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##
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default CONFIG_UDELAY_TSC=1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=5 # TODO?
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##
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## Build code to export a CMOS option table
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##
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# default HAVE_OPTION_TABLE=0
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 64 * 1024
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default FALLBACK_SIZE = 128 * 1024
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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# default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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##
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## The default compiler
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##
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default CROSS_COMPILE=""
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=9
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=9
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# VGA Console
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# default CONFIG_CONSOLE_VGA=1
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# default CONFIG_PCI_ROM_RUN=1
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end
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@ -0,0 +1,53 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||||
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* the Free Software Foundation; either version 2 of the License, or
|
||||||
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
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* GNU General Public License for more details.
|
||||||
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*
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||||||
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* You should have received a copy of the GNU General Public License
|
||||||
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* along with this program; if not, write to the Free Software
|
||||||
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
|
||||||
|
#include "arch/i386/lib/console.c"
|
||||||
|
#include "ram/ramtest.c"
|
||||||
|
#include "northbridge/amd/gx1/raminit.c"
|
||||||
|
#include "superio/nsc/pc87351/pc87351_early_serial.c"
|
||||||
|
#include "cpu/x86/bist.h"
|
||||||
|
|
||||||
|
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
|
||||||
|
|
||||||
|
static void main(unsigned long bist)
|
||||||
|
{
|
||||||
|
/* Initialize the serial console. */
|
||||||
|
pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||||
|
uart_init();
|
||||||
|
console_init();
|
||||||
|
|
||||||
|
/* Halt if there was a built in self test failure. */
|
||||||
|
report_bist_failure(bist);
|
||||||
|
|
||||||
|
/* Initialize RAM. */
|
||||||
|
sdram_init();
|
||||||
|
|
||||||
|
/* Check whether RAM works. */
|
||||||
|
/* ram_check(0x00000000, 0x4000); */
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the LinuxBIOS project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern struct chip_operations mainboard_asi_mb_5blmp_ops;
|
||||||
|
|
||||||
|
struct mainboard_asi_mb_5blmp_config {
|
||||||
|
int nothing;
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,39 @@
|
||||||
|
/* TODO: This is currently copied from the IEI NOVA-4899R target, but it's
|
||||||
|
* quite surely wrong for this board. It gets me further in the boot process
|
||||||
|
* than using no irq_tables.c file at all, though!
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* TODO: Add license header. */
|
||||||
|
|
||||||
|
#include <arch/pirq_routing.h>
|
||||||
|
|
||||||
|
const struct irq_routing_table intel_irq_routing_table = {
|
||||||
|
PIRQ_SIGNATURE, /* u32 signature */
|
||||||
|
PIRQ_VERSION, /* u16 version */
|
||||||
|
32+16*5, /* there can be total 5 devices on the bus */
|
||||||
|
0x00, /* Where the interrupt router lies (bus) */
|
||||||
|
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||||
|
0xe00, /* IRQs devoted exclusively to PCI usage */
|
||||||
|
0x1078, /* Vendor */
|
||||||
|
0x0002, /* Device */
|
||||||
|
0, /* Crap (miniport) */
|
||||||
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||||
|
0x2d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||||
|
{
|
||||||
|
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||||
|
// USB
|
||||||
|
{0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||||
|
// eth0
|
||||||
|
{0x00,(0x0a<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x3, 0x0},
|
||||||
|
// eth1
|
||||||
|
{0x00,(0x0b<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x2, 0x0},
|
||||||
|
// eth2
|
||||||
|
{0x00,(0x0c<<3)|0x0, {{0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x1, 0x0},
|
||||||
|
// PCI slot
|
||||||
|
{0x00,(0x0f<<3)|0x0, {{0x04, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||||
|
}
|
||||||
|
};
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the LinuxBIOS project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/device.h>
|
||||||
|
#include "chip.h"
|
||||||
|
|
||||||
|
struct chip_operations mainboard_asi_mb_5blmp_ops = {
|
||||||
|
CHIP_NAME("ASI/BCom MB-5BLMP Mainboard")
|
||||||
|
};
|
||||||
|
|
||||||
|
|
@ -0,0 +1,43 @@
|
||||||
|
##
|
||||||
|
## This file is part of the LinuxBIOS project.
|
||||||
|
##
|
||||||
|
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||||
|
##
|
||||||
|
## This program is free software; you can redistribute it and/or modify
|
||||||
|
## it under the terms of the GNU General Public License as published by
|
||||||
|
## the Free Software Foundation; either version 2 of the License, or
|
||||||
|
## (at your option) any later version.
|
||||||
|
##
|
||||||
|
## This program is distributed in the hope that it will be useful,
|
||||||
|
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
## GNU General Public License for more details.
|
||||||
|
##
|
||||||
|
## You should have received a copy of the GNU General Public License
|
||||||
|
## along with this program; if not, write to the Free Software
|
||||||
|
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
##
|
||||||
|
|
||||||
|
target mb_5blmp
|
||||||
|
mainboard asi/mb_5blmp
|
||||||
|
|
||||||
|
option ROM_SIZE = (256 * 1024)
|
||||||
|
# option ROM_SIZE = (256 * 1024) - (32 * 1024)
|
||||||
|
# option FALLBACK_SIZE = (256 * 1024) - (32 * 1024)
|
||||||
|
|
||||||
|
romimage "normal"
|
||||||
|
option USE_FALLBACK_IMAGE = 0
|
||||||
|
option ROM_IMAGE_SIZE = 64 * 1024
|
||||||
|
option LINUXBIOS_EXTRA_VERSION = ".0Normal"
|
||||||
|
payload /tmp/filo.elf
|
||||||
|
end
|
||||||
|
|
||||||
|
romimage "fallback"
|
||||||
|
option USE_FALLBACK_IMAGE = 1
|
||||||
|
option ROM_IMAGE_SIZE = 64 * 1024
|
||||||
|
option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
|
||||||
|
payload /tmp/filo.elf
|
||||||
|
end
|
||||||
|
|
||||||
|
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||||
|
# buildrom ./linuxbios.rom ROM_SIZE "fallback"
|
||||||
Loading…
Reference in New Issue