GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/pcengines/apu2: change GPIO setting 

Change GPIO setting to use IOMUX to refer to GPIO by
IOMUX register as in BKDG for Family 16h Models 30h-3fh
Processor Rev 3.06.

Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Michał Żygowski 2018-07-27 15:59:51 +02:00 committed by Felix Held
parent 6838aaebf9
commit a4432f469a
3 changed files with 45 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mainboard/pcengines/apu2/gpio_ftns.c
View File

@ -19,19 +19,23 @@
#include "FchPlatform.h"
#include "gpio_ftns.h"
void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
{
u8 bdata;
u8 *memptr;
u32 bdata;
memptr = (u8 *)(base_addr + IOMUX_OFFSET + iomux_gpio);
*memptr = iomux_ftn;
bdata = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET
+ gpio));
/* out the data value to prevent glitches */
bdata |= (setting & GPIO_OUTPUT_ENABLE);
write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), bdata);
memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);
bdata = *memptr;
bdata &= 0x07;
bdata |= setting; /* set direction and data value */
*memptr = bdata;
/* set direction and data value */
bdata |= (setting & (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE
| GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE));
write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), bdata);
write8((volatile void *)(ACPI_MMIO_BASE + IOMUX_OFFSET + iomux_gpio),
iomux_ftn & 0x3);
}
int get_spd_offset(void)

13
src/mainboard/pcengines/apu2/gpio_ftns.h
View File

@ -16,7 +16,7 @@
#ifndef GPIO_FTNS_H
#define GPIO_FTNS_H
void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
int get_spd_offset(void);
#define IOMUX_OFFSET 0xD00
@ -27,6 +27,7 @@ int get_spd_offset(void);
// http://www.pcengines.ch/schema/apu2c.pdf
// http://www.pcengines.ch/schema/apu3a.pdf
//
#define IOMUX_GPIO_22 0x09 // MODESW (APU5)
#define IOMUX_GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5)
#define IOMUX_GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5)
#define IOMUX_GPIO_49 0x40 // STRAP0
@ -41,6 +42,7 @@ int get_spd_offset(void);
#define IOMUX_GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5)
#define IOMUX_GPIO_71 0x4D // PROCHOT
#define GPIO_22 0x24 // MODESW (APU5)
#define GPIO_32 0x164 // MODESW (SIMSWAP2 on APU5)
#define GPIO_33 0x168 // SIMSWAP (SIMSWAP3 on APU5)
#define GPIO_49 0x100 // STRAP0
@ -55,9 +57,10 @@ int get_spd_offset(void);
#define GPIO_68 0x120 // PE4_WDIS (SIMSWAP1 on APU5)
#define GPIO_71 0x134 // PROCHOT
#define GPIO_OUTPUT_ENABLE 23
#define GPIO_OUTPUT_VALUE 22
#define GPIO_PULL_DOWN_ENABLE 21
#define GPIO_PULL_UP_ENABLE 20
#define GPIO_OUTPUT_ENABLE BIT23
#define GPIO_OUTPUT_VALUE BIT22
#define GPIO_PULL_DOWN_ENABLE BIT21
#define GPIO_PULL_UP_ENABLE BIT20
#define GPIO_PIN_STS BIT16
#endif /* GPIO_FTNS_H */

43
src/mainboard/pcengines/apu2/romstage.c
View File

@ -113,42 +113,45 @@ static void early_lpc_init(void)
//
// Configure output disabled, value low, pull up/down disabled
//
if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {
configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting);
}
if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) ||
IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
configure_gpio(ACPI_MMIO_BASE,
IOMUX_GPIO_32, Function0, GPIO_32, setting);
configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
}
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
configure_gpio(IOMUX_GPIO_49, Function2, GPIO_49, setting);
configure_gpio(IOMUX_GPIO_50, Function2, GPIO_50, setting);
configure_gpio(IOMUX_GPIO_71, Function0, GPIO_71, setting);
//
// Configure output enabled, value low, pull up/down disabled
//
setting = 0x1 << GPIO_OUTPUT_ENABLE;
setting = GPIO_OUTPUT_ENABLE;
if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
configure_gpio(ACPI_MMIO_BASE,
IOMUX_GPIO_33, Function0, GPIO_33, setting);
configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
}
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
configure_gpio(IOMUX_GPIO_57, Function1, GPIO_57, setting);
configure_gpio(IOMUX_GPIO_58, Function1, GPIO_58, setting);
configure_gpio(IOMUX_GPIO_59, Function3, GPIO_59, setting);
//
// Configure output enabled, value high, pull up/down disabled
//
setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE;
if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {
configure_gpio(ACPI_MMIO_BASE,
IOMUX_GPIO_32, Function0, GPIO_32, setting);
configure_gpio(ACPI_MMIO_BASE,
IOMUX_GPIO_33, Function0, GPIO_33, setting);
configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
}
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);
configure_gpio(IOMUX_GPIO_51, Function2, GPIO_51, setting);
configure_gpio(IOMUX_GPIO_55, Function3, GPIO_55, setting);
configure_gpio(IOMUX_GPIO_64, Function2, GPIO_64, setting);
configure_gpio(IOMUX_GPIO_68, Function0, GPIO_68, setting);
}