GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

soc/intel/apollolake: Fix issues detected by checkpatch

Browse source 
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: switch and case should be at the same indent
ERROR: do not use assignment in if condition
WARNING: Statements terminations use 1 semicolon
WARNING: unnecessary whitespace before a quoted newline
WARNING: else is not generally useful after a break or return

TEST=Build for reef

Change-Id: I5486936dbf19b066c76179d929660affa1da5f16
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18727
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2017-03-09 10:45:02 -08:00 committed by Martin Roth
parent 2d154e8213
commit a444753596
4 changed files with 39 additions and 39 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/soc/intel/apollolake/acpi.c
View file

@ -58,7 +58,7 @@ static int acpi_sci_irq(void)
static unsigned long acpi_madt_irq_overrides(unsigned long current)
{
int sci = acpi_sci_irq();
uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;;
uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;
/* INT_SRC_OVR */
current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);

22
src/soc/intel/apollolake/nhlt.c
View file

@ -183,17 +183,17 @@ static const struct nhlt_endp_descriptor max98357_descriptors[] = {
int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels)
{
switch (num_channels) {
case 1:
return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors,
ARRAY_SIZE(dmic_1ch_descriptors));
case 2:
return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors,
ARRAY_SIZE(dmic_2ch_descriptors));
case 4:
return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors,
ARRAY_SIZE(dmic_4ch_descriptors));
default:
return -1;
case 1:
return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors,
ARRAY_SIZE(dmic_1ch_descriptors));
case 2:
return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors,
ARRAY_SIZE(dmic_2ch_descriptors));
case 4:
return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors,
ARRAY_SIZE(dmic_4ch_descriptors));
default:
return -1;
}
}

51
src/soc/intel/apollolake/romstage.c
View file

@ -136,38 +136,37 @@ static bool punit_init(void)
reg = read32(bios_rest_cpl);
if (reg == 0xffffffff) {
/* P-unit not found */
printk(BIOS_DEBUG, "Punit MMIO not available \n");
printk(BIOS_DEBUG, "Punit MMIO not available\n");
return false;
} else {
/* Set Punit interrupt pin IPIN offset 3D */
pci_write_config8(PUNIT_DEVFN, PCI_INTERRUPT_PIN, 0x2);
}
/* Set Punit interrupt pin IPIN offset 3D */
pci_write_config8(PUNIT_DEVFN, PCI_INTERRUPT_PIN, 0x2);
/* Set PUINT IRQ to 24 and INTPIN LOCK */
write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ),
PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
PUINT_THERMAL_DEVICE_IRQ_LOCK);
/* Set PUINT IRQ to 24 and INTPIN LOCK */
write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ),
PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
PUINT_THERMAL_DEVICE_IRQ_LOCK);
data = read32((void *)(MCH_BASE_ADDR + 0x7818));
data &= 0xFFFFE01F;
data |= 0x20 | 0x200;
write32((void *)(MCH_BASE_ADDR + 0x7818), data);
data = read32((void *)(MCH_BASE_ADDR + 0x7818));
data &= 0xFFFFE01F;
data |= 0x20 | 0x200;
write32((void *)(MCH_BASE_ADDR + 0x7818), data);
/* Stage0 BIOS Reset Complete (RST_CPL) */
write32(bios_rest_cpl, 0x1);
/* Stage0 BIOS Reset Complete (RST_CPL) */
write32(bios_rest_cpl, 0x1);
/*
* Poll for bit 8 in same reg (RST_CPL).
* We wait here till 1 ms for the bit to get set.
*/
stopwatch_init_msecs_expire(&sw, 1);
while (!(read32(bios_rest_cpl) & 0x100)) {
if (stopwatch_expired(&sw)) {
printk(BIOS_DEBUG,
"Failed to set RST_CPL bit\n");
return false;
}
udelay(100);
/*
* Poll for bit 8 in same reg (RST_CPL).
* We wait here till 1 ms for the bit to get set.
*/
stopwatch_init_msecs_expire(&sw, 1);
while (!(read32(bios_rest_cpl) & 0x100)) {
if (stopwatch_expired(&sw)) {
printk(BIOS_DEBUG,
"Failed to set RST_CPL bit\n");
return false;
}
udelay(100);
}
return true;
}

3
src/soc/intel/apollolake/tsc_freq.c
View file

@ -37,7 +37,8 @@ void set_max_freq(void)
eax = cpuid_eax(CPUID_LEAF_PM);
msr = rdmsr(MSR_IA32_MISC_ENABLES);
if (!(eax &= 0x2) && ((msr.hi & APL_BURST_MODE_DISABLE) == 0)) {
eax &= 0x2;
if ((!eax) && ((msr.hi & APL_BURST_MODE_DISABLE) == 0)) {
/* Burst Mode has been factory configured as disabled
* and is not available in this physical processor
* package.